A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. - Hyungmin Jin; Jindo Byun; Hyunyoon Cho; Hojun Yoon; Jin-Hee Park; Kyoungsoo Kim; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; Sang-Hyun Lee (A-SSCC, 2021)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)