A novel ADPLL design using successive approximation frequency control. - Holger Eisenreich; Christian Mayr 001; Stephan Henker; Michael Wickert; René Schüffny (Microelectron. J., 2009)

Low power design of the X-GOLD® SDR 20 baseband processor. - Wolfgang Raab; Jörg Berthold; J. A. Ulrich Hachmann; Dominik Langen; Michael Schreiner; Holger Eisenreich; Jens-Uwe Schluessler; Georg Ellguth (DATE, 2010)

Efficient compensation of delay variations in high-speed network-on-chip data links. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; René Schüffny (SoC, 2010)

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. - Sebastian Höppner; Chenming Shao; Holger Eisenreich; Georg Ellguth; Mario Ander; René Schüffny (ISCAS, 2012)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; Stefan Schiefer; René Schüffny (ECCTD, 2013)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. - Sebastian Höppner; Holger Eisenreich; Stephan Henker; Dennis Walter; Georg Ellguth; René Schüffny (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A compact on-chip IR-drop measurement system in 28 nm CMOS technology. - Sebastian Dietel; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stefan Hänzsche; Stephan Henker; René Schüffny; Tim Brauninger; Ulrich Fiedler (ISCAS, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

A deep-submicron CMOS flow for general-purpose timing-detection insertion. - Andreas Dixius; Dennis Walter; Sebastian Höppner; Holger Eisenreich; René Schüffny (MIXDES, 2015)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. - Heiner Bauer; Sebastian Höppner; Johannes Partzsch; Dennis Walter; Christian Mayr 001; Florian Schraut; Holger Eisenreich (NORCAS, 2017)

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. - Sebastian Höppner; Jörg Schreiter; Robert Niebsch; Stephan Scherzer; Ulrich Hensel; Jörg Winkler; Mario Orgis; Holger Eisenreich; Dennis Walter; Uwe Steeb; André Scharfe; Clifford Dmello; et al. (ESSDERC, 2019)

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology. - Florian Schraut; Holger Eisenreich; Sebastian Höppner; Christian Mayr 001 (ISCAS, 2019)

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. - Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Heiner Bauer; Farkas Csaszar; Robert Niebsch; Jörg Schreiter; Holger Eisenreich; Sebastian Höppner (COOL CHIPS, 2020)

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. - Sebastian Höppner; Holger Eisenreich; Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Jörg Schreiter; Thorsten Riedel; Heiner Bauer; Robert Niebsch; Stephan Scherzer; Thomas Hocker; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology. - Sabine Kolodinski; Holger Eisenreich; Steffen Lehmann; Johannes Müller (ICICDT, 2021)

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. - Heiner Bauer; Marco Stolba; Stefan Scholze; Dennis Walter; Christian Mayr 001; Alexander Oefelein; Sebastian Höppner; André Scharfe; Florian Schraut; Holger Eisenreich (ISOCC, 2023)

EdgeVision SoC: PPA-Impact of RTL-level Modifications. - Mikail Yayla; Clifford Leon Dmello; Georg Ellguth; Uwe Steeb; Tim Leuchter; Marcus Pietzsch; Holger Eisenreich (SOCC, 2024)