A system level HW/SW partitioning and optimization tool. - Markus Schwiegershausen; Holger Kropp; Peter Pirsch (EURO-DAC, 1996)

A CAD tool for the optimization of video signal processor architectures. - Holger Kropp; Markus Schwiegershausen; Peter Pirsch (ICASSP, 1996)

Implementation of pipelined multipliers on Xilinx FPGAs. - Tien-Toan Do; Holger Kropp; Markus Schwiegershausen; Peter Pirsch (FPL, 1997)

A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. - Tien-Toan Do; Holger Kropp; Carsten Reuter; Peter Pirsch (FPL, 1998)

The Video and Image Processing Emulation System VIPES. - Holger Kropp; Carsten Reuter; Peter Pirsch (International Workshop on Rapid System Prototyping, 1998)

An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. - Holger Kropp; Carsten Reuter; Matthias Wiege; Tien-Toan Do; Peter Pirsch (FPL, 1999)

A Mapping Methodology for Code Trees onto LUT-Based FPGAs. - Holger Kropp; Carsten Reuter (FPL, 2000)

Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes). - Carsten Reuter; Holger Kropp; Peter Pirsch (Informationstechnik Tech. Inform., 2000)

The Effect of FPGA Granularity on Video Codec Implementations. - Jörn Gause; Carsten Reuter; Holger Kropp; Peter Y. K. Cheung; Wayne Luk (FCCM, 2001)

Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. - Javier Martín-Langerwerf; Carsten Reuter; Holger Kropp; Peter Pirsch (IEEE International Workshop on Rapid System Prototyping, 2002)

Quellenmodell-Architekturen redundanz-reduzierender Codierungsverfahren aus LUT-basierten FPGAs. - Holger Kropp (2004)