A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays. - Robin Lee; Jung-Ping Yang; Chia-En Huang; Chih-Chieh Chiu; Wei-Shuo Kao; Hong-Chen Cheng; Hong-Jen Liao; Jonathan Chang (VLSIC, 2012)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)