Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (GCCE, 2016)

A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. - Xin-Yu Shih; Hong-Ru Chou (GCCE, 2017)

Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. - Xin-Yu Shih; Hong-Ru Chou (ICCE, 2017)

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches. - Xin-Yu Shih; Yue-Qu Liu; Hong-Ru Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. - Xin-Yu Shih; Hong-Ru Chou (ICT Express, 2018)

VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. - Xin-Yu Shih; Po-Chun Huang; Hong-Ru Chou (Integr., 2018)

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. - Xin-Yu Shih; Hong-Ru Chou (Integr., 2019)