An experimental 16-Mbit DRAM with reduced peak-current noise. - Daeje Chin; Changhyun Kim; Yunho Choi; Dong-Sun Min; Hong-Sun Hwang; Hoon Choi; Soo-In Cho; Tae-Young Chung; Chan J. Park; Yunseung Shin; Kwang Pyuk Suh; Yong E. Park (IEEE J. Solid State Circuits, 1989)

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. - Changhyun Kim; Kye-Hyun Kyung; W.-P. Jeong; J.-S. Kim; Byung-Sik Moon; Joon-Wan Chai; S.-M. Yim; Jung-Hwan Choi; K.-H. Han; C.-J. Park; Hong-Sun Hwang; H. Choi; et al. (IEEE J. Solid State Circuits, 1999)

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling. - Jin-Hyun Kim; Sua Kim; Woo-Seop Kim; Jung-Hwan Choi; Hong-Sun Hwang; Changhyun Kim; Suki Kim (IEEE J. Solid State Circuits, 2005)

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (ESSCIRC, 2010)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Satoru Yamada; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (IEICE Trans. Electron., 2011)

The classification methodology of chip quality using canonical correlation analysis-based variable selection on chip level data. - Ki-Hyun Kim; Hyung-Shin Kwon; Hee-Il Hong; Hong-Sun Hwang; Kang-Yong Cho; Gyo-Young Jin (IEEM, 2015)