An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. - Kuan-Yu Lin; Hong-Ting Lin; Tsung-Yi Ho (ASP-DAC, 2011)

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. - Yi-Lin Chuang; Hong-Ting Lin; Tsung-Yi Ho; Yao-Wen Chang; Diana Marculescu (ICCAD, 2011)

Pulsed-latch-based clock tree migration for dynamic power reduction. - Hong-Ting Lin; Yi-Lin Chuang; Tsung-Yi Ho (ISLPED, 2011)

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. - Kuan-Yu Lin; Hong-Ting Lin; Tsung-Yi Ho; Chia-Chun Tsai (ACM Trans. Design Autom. Electr. Syst., 2012)

Pulsed-Latch Utilization for Clock-Tree Power Optimization. - Hong-Ting Lin; Yi-Lin Chuang; Zong-Han Yang; Tsung-Yi Ho (IEEE Trans. Very Large Scale Integr. Syst., 2014)