Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. - Hong Wang 003; Qing Yang 001 (ICPP (1), 1991)

On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. - Qing Yang 001; Hong Wang 003 (ICPP (1), 1992)

A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors. - Qing Yang 001; Hong Wang 003 (IEEE Trans. Parallel Distributed Syst., 1993)

CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. - Hong Wang 003; Tong Sun 001; Qing Yang 001 (ISCA, 1995)

Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. - Hong Wang 003; Tong Sun 001; Qing Yang 001 (IEEE Trans. Computers, 1997)

Redundant Arithmetic Optimizations (Research Note). - Thomas Y. Yeh; Hong Wang 003 (Euro-Par, 2000)

Register Renaming and Scheduling for Dynamic Execution of Predicated Code. - Perry H. Wang; Hong Wang 003; Ralph-Michael Kling; Kalpana Ramakrishnan; John Paul Shen (HPCA, 2001)

Speculative precomputation: long-range prefetching of delinquent loads. - Jamison D. Collins; Hong Wang 003; Dean M. Tullsen; Christopher J. Hughes; Yong-Fong Lee; Daniel M. Lavery; John Paul Shen (ISCA, 2001)

Dynamic speculative precomputation. - Jamison D. Collins; Dean M. Tullsen; Hong Wang 003; John Paul Shen (MICRO, 2001)

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. - R. David Weldon; Steven S. Chang; Hong Wang 003; Gerolf Hoflehner; Perry H. Wang; Daniel M. Lavery; John Paul Shen (Interaction between Compilers and Computer Architectures, 2002)

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. - Perry H. Wang; Hong Wang 003; Jamison D. Collins; Ed Grochowski; Ralph-Michael Kling; John Paul Shen (HPCA, 2002)

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. - Shih-Wei Liao; Perry H. Wang; Hong Wang 003; John Paul Shen; Gerolf Hoflehner; Daniel M. Lavery (PLDI, 2002)

Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. - Hong Wang 003; Shiri Manor; Dave LaFollette; Nadav Nesher; Ku-jei King; Perry H. Wang; Shay Levy; Shai Satt; Gal Carmeli; Arjun Kapur; Ioannis Schoinas; Ed Rubinstein; et al. (ISPASS, 2003)

A framework for modeling and optimization of prescient instruction prefetch. - Tor M. Aamodt; Pedro Marcuello; Paul Chow; Antonio González 001; Per Hammarlund; Hong Wang 003; John Paul Shen (SIGMETRICS, 2003)

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (ASPLOS, 2004)

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. - Dongkeun Kim; Shih-Wei Liao; Perry H. Wang; Juan del Cuvillo; Xinmin Tian; Xiang Zou; Hong Wang 003; Donald Yeung; Milind Girkar; John Paul Shen (CGO, 2004)

Hardware Support for Prescient Instruction Prefetch. - Tor M. Aamodt; Paul Chow; Per Hammarlund; Hong Wang 003; John Paul Shen (HPCA, 2004)

Best of Both Latency and Throughput. - Ed Grochowski; Ronny Ronen; John Paul Shen; Hong Wang 003 (ICCD, 2004)

Control Flow Optimization Via Dynamic Reconvergence Prediction. - Jamison D. Collins; Dean M. Tullsen; Hong Wang 003 (MICRO, 2004)

Helper Threads via Virtual Multithreading. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (IEEE Micro, 2004)

A Dependency Chain Clustered Microarchitecture. - Satish Narayanasamy; Hong Wang 003; Perry H. Wang; John Paul Shen; Brad Calder (IPDPS, 2005)

Multiple Instruction Stream Processor. - Richard A. Hankins; Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Ryan N. Rakvic; Hong Wang 003; John Paul Shen (ISCA, 2006)

Sequencer virtualization. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Bernard Lint; Asit Mallick; Koichi Yamada; Hong Wang 003 (ICS, 2007)

EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Hong Jiang; Xinmin Tian; Milind Girkar; Nick Y. Yang; Guei-Yuan Lueh; Hong Wang 003 (PLDI, 2007)

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. - Henry Wong; Anne Bracy; Ethan Schuchman; Tor M. Aamodt; Jamison D. Collins; Perry H. Wang; Gautham N. Chinya; Ankur Khandelwal Groen; Hong Jiang; Hong Wang 003 (PACT, 2008)

Merge: a programming model for heterogeneous multi-core systems. - Michael D. Linderman; Jamison D. Collins; Hong Wang 003; Teresa H. Meng (ASPLOS, 2008)

Processor Performance Modeling using Symbolic Simulation. - Omid Azizi; Jamison D. Collins; Dinesh Patil; Hong Wang 003; Mark Horowitz (ISPASS, 2008)

CPR: Composable performance regression for scalable multiprocessor models. - Benjamin C. Lee; Jamison D. Collins; Hong Wang 003; David M. Brooks (MICRO, 2008)

Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. - Carlos Madriles; Carlos García Quiñones; F. Jesús Sánchez; Pedro Marcuello; Antonio González 001; Dean M. Tullsen; Hong Wang 003; John Paul Shen (IEEE Trans. Parallel Distributed Syst., 2008)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

Criticality-based optimizations for efficient load processing. - Samantika Subramaniam; Anne Bracy; Hong Wang 003; Gabriel H. Loh (HPCA, 2009)

BLoG: post-silicon bug localization in processors using bug localization graphs. - Sung-Boem Park; Anne Bracy; Hong Wang 003; Subhasish Mitra (DAC, 2010)

Intel nehalem processor core made FPGA synthesizable. - Graham Schelle; Jamison D. Collins; Ethan Schuchman; Perry H. Wang; Xiang Zou; Gautham N. Chinya; Ralf Plate; Thorsten Mattner; Franz Olbrich; Per Hammarlund; Ronak Singhal; Jim Brayton; et al. (FPGA, 2010)

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. - Guilherme Ottoni; Gautham N. Chinya; Gerolf Hoflehner; Jamison D. Collins; Amit Kumar; Ethan Schuchman; David R. Ditzel; Ronak Singhal; Hong Wang 003 (Conf. Computing Frontiers, 2011)

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. - Guilherme Ottoni; Thomas Hartin; Christopher T. Weaver; Jason Brandt; Belliappa Kuttanna; Hong Wang 003 (Conf. Computing Frontiers, 2011)

Bothnia: a dual-personality extension to the Intel integrated graphics driver. - Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Hong Jiang; Guei-Yuan Lueh; Thomas Piazza; Hong Wang 003 (ACM SIGOPS Oper. Syst. Rev., 2011)

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. - Lavanya Subramanian; Kaushik Vaidyanathan; Anant Nori; Sreenivas Subramoney; Tanay Karnik; Hong Wang 003 (DAC, 2018)

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. - Kunal Korgaonkar; Ishwar Bhati; Huichu Liu; Jayesh Gaur; Sasikanth Manipatruni; Sreenivas Subramoney; Tanay Karnik; Steven Swanson; Ian Young 001; Hong Wang 003 (ISCA, 2018)

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. - Anant Nori; Jayesh Gaur; Siddharth Rai; Sreenivas Subramoney; Hong Wang 003 (ISCA, 2018)

Tackling memory access latency through DRAM row management. - Sriseshan Srikanth; Lavanya Subramanian; Sreenivas Subramoney; Thomas M. Conte; Hong Wang 003 (MEMSYS, 2018)

MARS: Memory Aware Reordered Source. - Ishwar Bhati; Udit Dhawan; Jayesh Gaur; Sreenivas Subramoney; Hong Wang 003 (CoRR, 2018)

Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. - Dipan Kumar Mandal; Srivatsava Jandhyala; Om Ji Omer; Gurpreet S. Kalsi; Biji George; Gopi Neela; Santhosh Kumar Rethinagiri; Sreenivas Subramoney; Lance Hacking; Jim Radford; Eagle Jones; Belliappa Kuttanna; et al. (DATE, 2019)