Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips. - Tsung-Wei Huang; Hong-Yan Su; Tsung-Yi Ho (DAC, 2011)

SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding. - Hong-Yan Su; Chih-Hao Hsu; Yih-Lang Li (DATE, 2015)

A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding. - Hong-Yan Su; Chieh-Chu Chen; Yih-Lang Li; An-Chun Tu; Chuh-Jen Wu; Chen-Ming Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Pin accessibility evaluating model for improving routability of VLSI designs. - Hong-Yan Su; Shinichi Nishizawa; Yan-Shiun Wu; Jun Shiomi; Yih-Lang Li; Hidetoshi Onodera (SoCC, 2017)

MapReduce-based pattern classification for design space analysis. - Yan-Shiun Wu; Hong-Yan Su; Yi-Hsiang Chang; Rasit Onur Topaloglu; Yih-Lang Li (VLSI-DAT, 2018)

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (DAC, 2019)

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)