Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. - Hong-Yi Huang; Chung-Yu Wu (ISCAS, 1993)

Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic. - Chung-Yu Wu; Hong-Yi Huang (IEEE J. Solid State Circuits, 1993)

New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. - Hong-Yi Huang; Chung-Yu Wu (ISCAS, 1994)

Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. - Hong-Yi Huang; Jinn-Shyan Wang; Yuan-Hua Chu; Tain-Shun Wu; Kuo-Hsing Cheng; Chung-Yu Wu (ISCAS, 1995)

High-speed CMOS logic circuits in capacitor coupling technique. - Hong-Yi Huang; Teng-Neng Wang (ISCAS (4), 2001)

Threshold triggers and accelerator for deep submicron interconnection. - Hong-Yi Huang; Shih-Lun Chen (APCCAS (2), 2002)

Multiple bulk input differential logic. - Hong-Yi Huang; Jing-Fu Lin (APCCAS (1), 2002)

High-speed receivers for on-chip interconnections in deep-submicron process. - Hong-Yi Huang; Shih-Lun Chen (ICECS, 2002)

A time-delay-integration CMOS readout circuit for IR scanning. - Fu-Kai Tsai; Hong-Yi Huang; Li-Kuo Dai; Cheng-Der Chiang; Ping-Kuo Weng; Yung-Chung Chin (ICECS, 2002)

Input isolated sense amplifiers. - Hong-Yi Huang; Shih-Lun Chen (ISCAS (4), 2002)

CMOS bulk input technique. - Hong-Yi Huang; Jing-Fu Lin (ISCAS (3), 2002)

Low-power 2P2N SRAM with column hidden refresh. - Hong-Yi Huang; Hsuan-Yi Su (ISCAS (4), 2002)

A high-bandwidth wireless infrared receiver with feedforward offset extractor. - Chin-Shan Hsieh; Hong-Yi Huang; Jeng-Dang Juan; Ruey-Nan Yeh (ISCAS (1), 2003)

A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs. - Chun-Jen Huang; Hong-Yi Huang (ISCAS (1), 2004)

Design and application of CMOS bulk input scheme. - Hong-Yi Huang; Jing-Fu Lin (IEEE J. Solid State Circuits, 2004)

A low-jitter mutual-correlated pulsewidth control loop circuit. - Wei-Ming Lin; Hong-Yi Huang (IEEE J. Solid State Circuits, 2004)

Interconnect accelerating techniques for sub-100-nm gigascale systems. - Hong-Yi Huang; Shih-Lun Chen (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A 64-MHz 1920-MHz programmable spread-spectrum clock generator. - Hong-Yi Huang; Sheng-Fen Ho; Li-Wei Huang (ISCAS (4), 2005)

1-99% input duty 50% output duty cycle corrector. - Hong-Yi Huang; Chia-Ming Liang; Wei-Ming Chiu (ISCAS, 2006)

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. - Hong-Yi Huang; Bo-Ruei Wang; Jen-Chieh Liu (ISCAS, 2006)

On-chip bidirectional transceiver. - Hong-Yi Huang; Ching-Chieh Wu; Sen-Da Wu (ISCAS, 2006)

All-Digital PLL Using Pulse-Based DCO. - Hong-Yi Huang; Jen-Chieh Liu; Kuo-Hsing Cheng (ICECS, 2007)

A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. - Hong-Yi Huang; Sheng-Da Wu; Yi-Jui Tsai (ISCAS, 2007)

CMOS bulk input current switch logic circuit. - Hong-Yi Huang; Chun-Tsai Hung; Sheng-Chia Chiang (ICECS, 2008)

Simultaneous bidirectional transceiver with impedance matching. - Hong-Yi Huang; Ruei-Iun Pu; Ming-Ta Lee (ICECS, 2008)

Piecewise linear curvature-compensated CMOS bandgap reference. - Hong-Yi Huang; Ru-Jie Wang; Shih-Chiang Hsu (ICECS, 2008)

Dual band LNA/mixer using conjugate matching for implantable biotelemetry. - Wei-Chen Huang; Chen-Ming Hsu; Chien-Ming Lee; Hong-Yi Huang; Ching-Hsing Luo (ISCAS, 2008)

Low-power 50% duty cycle corrector. - Hong-Yi Huang; Chia-Ming Liang; Shi-Jia Sun (ISCAS, 2008)

A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. - Hong-Yi Huang; Li-Wei Huang; Wei-Sheng Tseng; Chih-Yuan Hsu (SoCC, 2008)

All digital time-to-digital converter using single delay-locked loop. - Hong-Yi Huang; Yi-Jui Tsai; Kung-Liang Ho; Chan-Yu Lin (SoCC, 2008)

Frequency multiplier using 50% duty cycle corrector. - Hong-Yi Huang; Chia-Ming Liang (IEICE Electron. Express, 2008)

Analysis and optimization of ring oscillator using sub-feedback scheme. - Hong-Yi Huang; Fu-Chien Tsai (DDECS, 2009)

0.5V 160-MHz 260uW all digital phase-locked loop. - Jen-Chieh Liu; Hong-Yi Huang; Wei-Bin Yang; Kuo-Hsing Cheng (DDECS, 2009)

Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications. - Shih-Lun Chen; Ho-Yin Lee; Chiung-An Chen; Hong-Yi Huang; Ching-Hsing Luo (IEEE Syst. J., 2009)

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. - Kuo-Hsing Cheng; Chang-Chien Hu; Jen-Chieh Liu; Hong-Yi Huang (DDECS, 2010)

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications. - Chia-Lin Chang; Chih-Wei Chang; Hong-Yi Huang; Chen-Ming Hsu; Chia-Hsuan Huang; Jin-Chern Chiou; Ching-Hsing Luo (Sensors, 2010)

Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor. - Wei-Song Wang; Wei-Ting Kuo; Hong-Yi Huang; Ching-Hsing Luo (Sensors, 2010)

Variable-Latency Floating-Point Multipliers for Low-Power Applications. - Shiann-Rong Kuang; Jiun-Ping Wang; Hong-Yi Huang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

All digital phase-locked loop using active inductor oscillator and novel locking algorithm. - Tzu-Chi Huang; Hong-Yi Huang; Jen-Chieh Liu; Kuo-Hsing Cheng; Ching-Hsing Luo (ISCAS, 2011)

Differential bidirectional transceiver for on-chip long wires. - Hong-Yi Huang; Ruei-Iun Pu (Microelectron. J., 2011)

An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs). - Chiung-An Chen; Shih-Lun Chen; Hong-Yi Huang; Ching-Hsing Luo (Sensors, 2011)

Real-Time Telemetry System for Amperometric and Potentiometric Electrochemical Sensors. - Wei-Song Wang; Hong-Yi Huang; Shu-Chun Chen; Kuo-Chuan Ho; Chia-Yu Lin; Tse-Chuan Chou; Chih-Hsien Hu; Wen-Fong Wang; Cheng-Feng Wu; Ching-Hsing Luo (Sensors, 2011)

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. - Kuo-Hsing Cheng; Jen-Chieh Liu; Hong-Yi Huang; Yu-Liang Li; Yong-Jhen Jhu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications. - Shih-Lun Chen; Hong-Yi Huang; Ching-Hsing Luo (IEEE Trans. Circuits Syst. Video Technol., 2011)

Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images. - Shih-Lun Chen; Hong-Yi Huang; Ching-Hsing Luo (IEEE Trans. Circuits Syst. Video Technol., 2011)

A low power analog front-end (AFE) circuit dedicated for driving bio-electrochemical sensors and peripheral devices. - Wei-Jhe Ma; Ching-Hsing Luo; Hong-Yi Huang (BioCAS, 2012)

A low voltage sigma delta modulator for temperature sensor. - Yi-Hsiang Juan; Ching-Hsing Luo; Hong-Yi Huang (DDECS, 2012)

CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes. - Hong-Yi Huang; Shiun-Dian Jan; Yang Chou; Cheng-Yu Chen (IEICE Trans. Electron., 2012)

An MICS band frequency synthesizer using active inductor and auto-calibration scheme. - Hong-Yi Huang; Chun-Chieh Wu; Ching-Hsing Luo (Microelectron. J., 2012)

An Efficient Micro Control Unit with a Reconfigurable Filter Design for Wireless Body Sensor Networks (WBSNs). - Chiung-An Chen; Shih-Lun Chen; Hong-Yi Huang; Ching-Hsing Luo (Sensors, 2012)

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. - Kuo-Hsing Cheng; Jen-Chieh Liu; Hong-Yi Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

External capacitorless low dropout linear regulator using cascode structure. - Hong-Yi Huang; Cheng-Yu Chen; Kuo-Hsing Cheng (DDECS, 2013)

Indoor energy harvesting using photovoltaic cell for battery recharging. - Hong-Yi Huang; Chinet Otic Mocorro; Julyver Pinaso; Kuo-Hsing Cheng (DDECS, 2013)

A low jitter delay-locked-loop applied for DDR4. - Yo-Hao Tu; Kuo-Hsing Cheng; Hsiang-Yun Wei; Hong-Yi Huang (DDECS, 2013)

Adaptive successive approximation ADC for biomedical acquisition system. - Hui-Wen Chang; Hong-Yi Huang; Yi-Hsiang Juan; Wei-Song Wang; Ching-Hsing Luo (Microelectron. J., 2013)

A Low-Power Bio-Potential Acquisition System with Flexible PDMS Dry Electrodes for Portable Ubiquitous Healthcare Applications. - Chih-Yuan Chen; Chia-Lin Chang; Chih-Wei Chang; Shin-Chi Lai; Tsung-Fu Chien; Hong-Yi Huang; Jin-Chern Chiou; Ching-Hsing Luo (Sensors, 2013)

A 64-MHz∼640-MHz 64-phase clock generator. - Hong-Yi Huang; Jen-Chieh Liu; Shi-Jia Sun; Cheng-Hao Fu; Kuo-Hsing Cheng (DDECS, 2014)

A low supply voltage synchronous mirror delay with quadrature phase output. - Yo-Hao Tu; Kuo-Hsing Cheng; Chih-Hsun Hsu; Hong-Yi Huang (DDECS, 2014)

Analysis and design of a 1.3-mW current-reuse RF front-end for the MICS band. - Hugo Cruz; Hong-Yi Huang; Shuenn-Yuh Lee; Ching-Hsing Luo (ISCAS, 2014)

A radio-controlled receiver for clocks/watches and alarm applications. - Jen-Chieh Liu; Huan-Ke Chiu; Jia-Hung Peng; Yuan-Hua Chu; Hong-Yi Huang (ISCAS, 2014)

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. - Hong-Yi Huang; Jen-Chieh Liu; Pei-Ying Lee; Kun-Yuan Chen; Jin-Sheng Chen; Kuo-Hsing Cheng; Tzuen-Hsi Huang; Ching-Hsing Luo; Jin-Chern Chiou (DDECS, 2015)

Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking. - Hong-Yi Huang; Gene Fe P. Palencia; Da-Kai Chen; Wei-Hsuan Huang (DDECS, 2015)

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. - Yo-Hao Tu; Kuo-Hsing Cheng; Yian-An Lin; Hong-Yi Huang (DDECS, 2015)

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. - Hugo Cruz; Hong-Yi Huang; Shueen-Yu Lee; Ching-Hsing Luo (VLSI-DAT, 2015)

A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm. - Hugo Cruz; Hong-Yi Huang; Shuenn-Yuh Lee; Ching-Hsing Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Gm-C filter with automatic calibration scheme. - Hong-Yi Huang; Kun-Yuan Chen; Jia-Hao Xie; Ming-Ta Lee; Hao-Chiao Hong; Kuo-Hsing Cheng (DDECS, 2016)

Low-voltage indoor energy harvesting using photovoltaic cell. - Hong-Yi Huang; Shao-Zu Yen; Jhen-Hong Chen; Hao-Chiao Hong; Kuo-Hsing Cheng (DDECS, 2016)

A chaotically injected timing technique for ring-based oscillators. - Yo-Hao Tu; Kuo-Hsing Cheng; Wei-Ren Wang; Jen-Chieh Liu; Hong-Yi Huang (DDECS, 2016)

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. - Yo-Hao Tu; Jen-Chieh Liu; Kuo-Hsing Cheng; Hong-Yi Huang; Chang-Chien Hu (IEICE Electron. Express, 2016)

A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters. - Yi-Hsiang Juan; Hong-Yi Huang; Shin-Chi Lai; Wen-Ho Juang; Shuenn-Yuh Lee; Ching-Hsing Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A novel clock-pulse-width calibration technique for charge redistribution DACs. - Hugo Cruz; Hong-Yi Huang; Ching-Hsing Luo; Lih-Yih Chiou; Shuenn-Yuh Lee (ISCAS, 2017)

A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS. - Hugo Cruz; Hong-Yi Huang; Ching-Hsing Luo; Shuenn-Yuh Lee (IEEE Trans. Biomed. Circuits Syst., 2017)

CYUT Team2 SimpleText Shared Task Report in CLEF-2022. - Shih-Hung Wu; Hong-Yi Huang (CLEF (Working Notes), 2022)

SimpleText Best of Labs in CLEF-2022: Simplify Text Generation with Prompt Engineering. - Shih-Hung Wu; Hong-Yi Huang (CLEF, 2023)

A Prompt Engineering Approach to Scientific Text Simplification: CYUT at SimpleText2023 Task3. - Shih-Hung Wu; Hong-Yi Huang (CLEF (Working Notes), 2023)

A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System. - Kuo-Hsing Cheng; Chun-Yao Chang; Hong-Yi Huang; Yun-Teng Shih (ICECS, 2023)

A 1 50mA 20ns Settling Time Low Dropout Regulator. - Hong-Yi Huang; Yu-Ming Tsao; Angelo Nico M. Daroy; Kuo-Hsing Cheng (ICECS, 2023)

RF Energy Harvesting with Wide Input Power Range. - Hong-Yi Huang; Chun-Wei Wu; Nieva M. Mapula (ICECS, 2023)

Buck Converter with Variable Output Voltage for Dynamic Voltage Scaling (DVS) Applications. - Harreez M. Villaruz; Hong-Yi Huang; Nieva M. Mapula; Gene Fe P. Palencia (ISCIT, 2023)

A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique. - Hong-Yi Huang; Jen-Chieh Liu; Fu-Chien Tsai; Kun-Hua Lee; Kun-Yuan Chen (Circuits Syst. Signal Process., 2023)

Quaff: Quantized Parameter-Efficient Fine-Tuning under Outlier Spatial Stability Hypothesis. - Hong-Yi Huang; Dapeng Wu 001 (CoRR, 2025)