Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. - Chih-Hsiang Peng; Po-Chuan Lin; Shovan Barma; Jhing-Fa Wang; Hong-Yuan Peng; K. Bharanitharan; Ta-Wen Kuan (IET Comput. Digit. Tech., 2015)