Power-aware high level evaluation model of interconnect length of on-chip memory network topology. - Xiaojun Wang 005; Feng Shi 009; Yi-Zhuo Wang 001; Hong Zhang 036; Xu Chen 016; Wen-Fei Fu (Int. J. Comput. Sci. Eng., 2018)

KLSAT: An Application Mapping Algorithm Based on Kernighan-Lin Partition and Simulated Annealing for a Specific WK-Recursive NoC Architecture. - Xiaojun Wang 005; Feng Shi 009; Hong Zhang 036 (NPC, 2019)

A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory. - Xiaojun Wang 005; Feng Shi 009; Hong Zhang 036 (PAAP, 2019)

KGT: An Application Mapping Algorithm Based on Kernighan-Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture. - Hong Zhang 036; Xiaojun Wang 005 (ICIC (1), 2021)