1024-point pipeline FFT processor with pointer FIFOs based on FPGA. - Guanwen Zhong; Hongbin Zheng; ZhenHua Jin; Dihu Chen; Zhiyong Pang (VLSI-SoC, 2011)

A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis. - Hongbin Zheng; Qingrui Liu; Junyi Li; Dihu Chen; Zixin Wang (ASP-DAC, 2013)

High-level synthesis with behavioral level multi-cycle path analysis. - Hongbin Zheng; Swathi T. Gurumani; Liwei Yang; Deming Chen; Kyle Rupnow (FPL, 2013)

Fast and effective placement and routing directed high-level synthesis for FPGAs. - Hongbin Zheng; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (FPGA, 2014)

New solutions for system-level and high-level synthesis (Invited paper). - Wei Zuo; Hongbin Zheng; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (ISIC, 2014)

High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. - Hongbin Zheng; Swathi T. Gurumani; Liwei Yang; Deming Chen; Kyle Rupnow (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Optimizing Memory-Access Patterns for Deep Learning Accelerators. - Hongbin Zheng; Sejong Oh; Huiqing Wang; Preston Briggs; Jiading Gai; Animesh Jain; Yizhi Liu; Rich Heaton; Randy Huang; Yida Wang (CoRR, 2020)