In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. - Zhiting Lin; Honglan Zhan; Xuan Li; Chunyu Peng; Wenjuan Lu; Xiulong Wu; Junning Chen (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. - Zhiting Lin; Honglan Zhan; Zhongwei Chen; Chunyu Peng; Xiulong Wu; Wenjuan Lu; Qiang Zhao 007; Xuan Li; Junning Chen (IEEE J. Solid State Circuits, 2021)

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. - Zhiting Lin; Zhiyong Zhu; Honglan Zhan; Chunyu Peng; Xiulong Wu; Yuan Yao; Jianchao Niu; Junning Chen (IEEE J. Solid State Circuits, 2021)

MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies. - Hongwei Cui; Yujie Cui; Honglan Zhan; Shuhao Liang; Xianhua Liu 001; Chun Yang; Xu Cheng 001 (PACT, 2023)

A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation. - Hongwei Cui; Shuhao Liang; Yujie Cui; Weiqi Zhang; Honglan Zhan; Chun Yang; Xianhua Liu 001; Xu Cheng 001 (DATE, 2023)

High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. - Honglan Zhan; Chenxi Wang; Hongwei Cui; Xianhua Liu 001; Feng Liu; Xu Cheng 001 (DATE, 2023)

Multi: Reduce Energy Overhead of Criticality-Aware Dynamic Instruction Scheduling for Energy Efficiency. - Honglan Zhan; Chenxi Wang; Xin Wang; Chun Yang; Xianhua Liu 001; Xu Cheng 001 (ICCD, 2024)