A novel vision chip architecture for image recognition based on convolutional neural network. - Honglong Li; Zhongxing Zhang; Jie Yang 033; Liyuan Liu; Nanjian Wu (ASICON, 2015)

High-speed object detection based on a hierarchical parallel vision chip. - Zhongxing Zhang; Jie Yang 033; Honglong Li; Liyuan Liu; Jian Liu 021; Nanjian Wu (ASICON, 2015)

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. - Qian Di; Zhongxing Zhang; Honglong Li; Zhao Zhang 004; Peng Feng 001; Nanjian Wu (IEICE Electron. Express, 2019)

ViP: A Hierarchical Parallel Vision Processor for Hybrid Vision Chip. - Xuemin Zheng; Li Cheng 005; Mingxin Zhao; Qian Luo; Honglong Li; Runjiang Dou; Shuangming Yu; Nanjian Wu; Liyuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Hierarchical Parallel Vision Processor for High-Speed Ship Detection. - Mengmeng Xu; Zhongxing Zhang; Honglong Li; Qian Luo; Runjiang Dou; Liyuan Liu; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)