A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. - Hongil Yoon; Gi-Won Cha; Changsik Yoo; Nam-Jong Kim; Keum-Yong Kim; Chang Ho Lee; Kyu-Nam Lim; Kyuchan Lee; Jun-Young Jeon; Tae Sung Jung; Hongsik Jeong; Tae-Young Chung; et al. (IEEE J. Solid State Circuits, 1999)

A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme. - Gitae Jeong; Wooyoung Cho; Sujin Ahn; Hongsik Jeong; Gwanhyeob Koh; Youngnam Hwang; Kinam Kim (IEEE J. Solid State Circuits, 2003)

Emerging memory technologies. - Kinam Kim; Gitae Jeong; Hongsik Jeong; Sungyung Lee (CICC, 2005)

A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). - Woo Yeong Cho; Beak-Hyung Cho; Byung-Gil Choi; Hyung-Rok Oh; Sangbeom Kang; Ki-Sung Kim; Kyung-Hee Kim; Du-Eung Kim; Choong-Keun Kwak; Hyun-Geun Byun; Youngnam Hwang; SuJin Ahn; et al. (IEEE J. Solid State Circuits, 2005)

Enhanced write performance of a 64-mb phase-change random access memory. - Hyung-Rok Oh; Beak-Hyung Cho; Woo Yeong Cho; Sangbeom Kang; Byung-Gil Choi; Hye-Jin Kim; Ki-Sung Kim; Du-Eung Kim; Choong-Keun Kwak; Hyun-Geun Byun; Gitae Jeong; Hong-Sik Jeong; et al. (IEEE J. Solid State Circuits, 2006)

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput. - KwangJin Lee; Beak-Hyung Cho; Woo-Yeong Cho; Sangbeom Kang; Byung-Gil Choi; Hyung-Rok Oh; Changsoo Lee; Hye-Jin Kim; Joon-min Park; Qi Wang; Mu-Hui Park; Yu-Hwan Ro; et al. (ISSCC, 2007)

A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. - Sangbeom Kang; Woo Yeong Cho; Beak-Hyung Cho; KwangJin Lee; Changsoo Lee; Hyung-Rok Oh; Byung-Gil Choi; Qi Wang; Hye-Jin Kim; Mu-Hui Park; Yu-Hwan Ro; Suyeon Kim; et al. (IEEE J. Solid State Circuits, 2007)

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput. - KwangJin Lee; Beak-Hyung Cho; Woo-Yeong Cho; Sangbeom Kang; Byung-Gil Choi; Hyung-Rok Oh; Changsoo Lee; Hye-Jin Kim; Joon-min Park; Qi Wang; Mu-Hui Park; Yu-Hwan Ro; et al. (IEEE J. Solid State Circuits, 2008)

Emulation of spike-timing dependent plasticity in nano-scale phase change memory. - Dae-Hwan Kang; Hyun-Goo Jun; Kyung-Chang Ryoo; Hongsik Jeong; Hyunchul Sohn (Neurocomputing, 2015)

High density PCM(phase change memory) technology. - Hongsik Jeong (ISOCC, 2016)

Modeling of data retention statistics of phase-change memory with confined- and mushroom-type cells. - Yongwoo Kwon; Byoungnam Park; Heesun Yang; Jin-Ha Hwang; Dae-Hwan Kang; Hongsik Jeong; Yunheub Song (Microelectron. Reliab., 2016)

A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC. - Seongyeon Yu; Namwook Hur; Wansun Kim; Mann-Ho Cho; Hyunchul Sohn; Joonki Suh; Hongsik Jeong; Jong-Hyeok Yoon (ISOCC, 2023)