CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (MEMSYS, 2019)

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Jian-Wei Su; Yen-Chi Chou; Wei-Hsing Huang; Ta-Wei Liu; Ruhui Liu; Meng-Fan Chang; Shimeng Yu (DAC, 2020)

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (DATE, 2020)

XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (ICCAD, 2020)

MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Shimeng Yu (ISCAS, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. - Wonbo Shim; Hongwu Jiang; Xiaochen Peng; Shimeng Yu (MEMSYS, 2020)

8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. - Hongwu Jiang; Rui Liu 005; Shimeng Yu (MWSCAS, 2020)

CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (IEEE Trans. Computers, 2020)

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (AICAS, 2021)

Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. - Wantong Li; Shanshi Huang; Xiaoyu Sun 001; Hongwu Jiang; Shimeng Yu (CICC, 2021)

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. - Wantong Li; Xiaoyu Sun 001; Hongwu Jiang; Shanshi Huang; Shimeng Yu (ESSDERC, 2021)

Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. - Shanshi Huang; Xiaochen Peng; Hongwu Jiang; Yandong Luo; Shimeng Yu (ISCAS, 2021)

Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. - Shanshi Huang; Hongwu Jiang; Shimeng Yu (NVMSA, 2021)

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (Frontiers Artif. Intell., 2021)

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. - Xiaochen Peng; Shanshi Huang; Hongwu Jiang; Anni Lu; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. - Wantong Li; James Read; Hongwu Jiang; Shimeng Yu (ESSCIRC, 2022)

A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. - Hongwu Jiang; Wantong Li; Shanshi Huang; Shimeng Yu (VLSI Technology and Circuits, 2022)

Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. - Hongwu Jiang; Wantong Li; Shanshi Huang; Stefan Cosemans; Francky Catthoor; Shimeng Yu (IEEE Des. Test, 2022)

MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine. - Wantong Li; James Read; Hongwu Jiang; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. - Wantong Li; Xiaoyu Sun 001; Shanshi Huang; Hongwu Jiang; Shimeng Yu (IEEE J. Solid State Circuits, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2022)

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. - Shanshi Huang; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2023)

Architecture and Circuit Design Optimization for Compute-In-Memory. - Hongwu Jiang (2023)

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. - Hongwu Jiang; Shanshi Huang; Wantong Li; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks. - Xipeng Lin; Shanshi Huang; Hongwu Jiang (ICCAD, 2024)

OpenC2: An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory Macro. - Tianchu Dong; Shaoxuan Li; Yihang Zuo; Hongwu Jiang; Yuzhe Ma; Shanshi Huang (DATE, 2025)