An Online Multidomain Validation Method for Wireless Sensor Nodes. - Changjian Deng; Dongyi Chen; Heng Zhang; Hongyang Hu; Jianzhong Lin (Int. J. Distributed Sens. Networks, 2013)

Study of total ionizing dose induced read bit errors in magneto-resistive random access memory. - Haohao Zhang; Jinshun Bi; Haibin Wang; Hongyang Hu; Jin Li; Lanlong Ji; Ming Liu 022 (Microelectron. Reliab., 2016)

A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference. - Hongyang Hu; Zi Wang; Xiaoxin Xu; Kai Xi; Kun Zhang; Junyu Zhang; Chunmeng Dou (APCCAS, 2022)

High-speed and low-power embedded TEC BCH scheme for ReRAM array. - Kun Zhang; Haiyang Liu; Xu Zheng; Xiaoxin Xu; Hongyang Hu; Junyu Zhang (IEICE Electron. Express, 2023)

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. - Hongyang Hu; Xiwei Wang; Zi Wang; Haiyang Zhou; Danian Dong; Jinshan Yue; Wan Pang; Xiaoxin Xu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. - Weizeng Li; Linfang Wang; Zhi Li 062; Wang Ye; Zhidao Zhou; Haiyang Zhou; Hanghang Gao; Jinshan Yue; Hongyang Hu; Fengman Liu; Qing Luo; Chunmeng Dou (ISCAS, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering. - Haiyang Zhou; Hongyang Hu; Jinshan Yue; Hanghang Gao; Yuanlu Xie; Xiaoxin Xu; Chunmeng Dou; Ming Liu 022 (DAC, 2025)

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. - Wang Ye; Hanghang Gao; Zhidao Zhou; Linfang Wang; Weizeng Li; Zhi Li 062; Jinshan Yue; Xiaoxin Xu; Jianguo Yang; Hongyang Hu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Development of an explainable machine learning model for predicting device-related pressure injuries in clinical settings. - Yijie Qian; Hongying Pan; Jun Chen; Hongyang Hu; Mei Fang; Chen Huang; Yihong Xu; Yang Gao (BMC Medical Informatics Decis. Mak., 2025)