A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. - Zheng Sun 001; Hanli Liu; Dexian Tang; Hongye Huang; Tohru Kaneko; Rui Wu 001; Wei Deng 001; Kenichi Okada 001 (ESSCIRC, 2018)

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Wei Deng 001; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Zhijie Chen; Wei Deng 001; Rui Wu 001; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO. - Zheng Sun 001; Hanli Liu; Dingxin Xu; Hongye Huang; Bangan Liu; Zheng Li 021; Jian Pang; Teruki Someya; Atsushi Shirane (ESSCIRC, 2019)

A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2019)

A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (ISSCC, 2019)

A 265- $ mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. - Hanli Liu; Atsushi Shirane; Kenichi Okada 001; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya (IEEE J. Solid State Circuits, 2019)

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. - Jian Pang; Rui Wu 001; Yun Wang 008; Masato Dome; Hisashi Kato; Hongye Huang; Aravind Tharayil Narayanan; Hanli Liu; Bangan Liu; Takeshi Nakamura; Takuya Fujimura; Masaru Kawabuchi; et al. (IEEE J. Solid State Circuits, 2019)

A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. - Zheng Li 021; Jian Pang; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Joshua Alvin; Bangan Liu; Zheng Sun 001; Hongye Huang; et al. (ASP-DAC, 2020)

A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (VLSI Circuits, 2020)

A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. - Zheng Sun 001; Dingxin Xu; Hongye Huang; Zheng Li 021; Hanli Liu; Bangan Liu; Jian Pang; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2020)

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (IEEE J. Solid State Circuits, 2020)

A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. - Zheng Sun 001; Dingxin Xu; Junjun Qiu; Zezheng Liu; Yuncheng Zhang; Hongye Huang; Hanli Liu; Bangan Liu; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2021)

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2021)

A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Weichu Chen; Yun Wang 008; Dongwon You; et al. (VLSI Circuits, 2021)

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (IEEE J. Solid State Circuits, 2021)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. - Zheng Sun 001; Hanli Liu; Hongye Huang; Dexian Tang; Dingxin Xu; Tohru Kaneko; Zheng Li 021; Jian Pang; Rui Wu 001; Wei Deng 001; Atsushi Shirane; Kenichi Okada 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (CICC, 2023)

A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. - Junjun Qiu; Wenqian Wang; Zheng Sun 001; Bangan Liu; Yuncheng Zhang; Dingxin Xu; Hongye Huang; Ashbir Aviat Fadila; Zezheng Liu; Waleed Madany; Yuang Xiong; Atsushi Shirane; et al. (ISSCC, 2023)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (VLSI Technology and Circuits, 2023)

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (ISSCC, 2024)

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (VLSI Technology and Circuits, 2024)

A synthesizable spread spectrum clock generator based on type-II/III fractional-N DPLL. - Waleed Madany; Hongye Huang; Bangan Liu; Ashbir Aviat Fadila; Zezheng Liu; Wenqian Wang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2024)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (IEEE J. Solid State Circuits, 2024)

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (ASP-DAC, 2025)

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. - Daxu Zhang; Dingxin Xu; Hongye Huang; Waleed Madany; Zezheng Liu; Wenqian Wang; Yuang Xiong; Ashbir Aviat Fadila; Duo Li; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (CICC, 2025)

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM. - Yuncheng Zhang; Zezheng Liu; Duo Li; Minzhe Tang; Yi Zhang 092; Hongye Huang; Dingxin Xu; Waleed Madany; Ashbir Aviat Fadila; Wenqian Wang; Yuang Xiong; Daxu Zhang; et al. (ISSCC, 2025)

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. - Hongye Huang; Ashbir Aviat Fadila; Dingxin Xu; Waleed Madany; Wenqian Wang; Zezheng Liu; Yuang Xiong; Tianshi Hu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (IEEE J. Solid State Circuits, 2025)

A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (IEEE J. Solid State Circuits, 2025)

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (IEEE J. Solid State Circuits, 2025)