Thermal modeling and management of DRAM memory systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Howard David; Zhao Zhang 010 (ISCA, 2007)

DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010; Howard David (ISPASS, 2007)

Memory Access Scheduling Schemes for Systems with Multi-Core Processors. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ICPP, 2008)

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Eugene Gorbatov; Howard David; Zhichun Zhu (MICRO, 2008)

Software thermal management of dram memory for multicore systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Eugene Gorbatov; Howard David; Zhao Zhang 010 (SIGMETRICS, 2008)

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ISCA, 2009)

Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture. - Kun Fang 005; Hongzhong Zheng; Zhichun Zhu (ICPP, 2010)

Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. - Hongzhong Zheng; Zhichun Zhu (IEEE Trans. Computers, 2010)

Thermal Modeling and Management of DRAM Systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010 (IEEE Trans. Computers, 2013)

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. - Kun Fang 005; Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (IEEE Trans. Computers, 2014)

FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration. - Krishna T. Malladi; Mu-Tien Chang; John Ping; Hongzhong Zheng (MASCOTS, 2015)

FlexDrive: A Framework to Explore NVMe Storage Solutions. - Krishna T. Malladi; Manu Awasthi; Hongzhong Zheng (HPCC/SmartCity/DSS, 2016)

DRAMPersist: Making DRAM Systems Persistent. - Krishna T. Malladi; Manu Awasthi; Hongzhong Zheng (MEMSYS, 2016)

DRAMScale: Mechanisms to Increase DRAM Capacity. - Krishna T. Malladi; Uksong Kang; Manu Awasthi; Hongzhong Zheng (MEMSYS, 2016)

Software-Defined Emulation Infrastructure for High Speed Storage. - Krishna T. Malladi; Manu Awasthi; Hongzhong Zheng (SYSTOR, 2016)

MEMRES: A Fast Memory System Reliability Simulator. - Shaodi Wang; Henry Chaohong Hu; Hongzhong Zheng; Puneet Gupta 001 (IEEE Trans. Reliab., 2016)

DRISA: a DRAM-based reconfigurable in-situ accelerator. - Shuangchen Li; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Yuan Xie 001 (MICRO, 2017)

FlashStorageSim: Performance Modeling for SSD Architectures. - Krishna T. Malladi; Mu-Tien Chang; Dimin Niu; Hongzhong Zheng (NAS, 2017)

Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache. - Tyler Stocksdale; Mu-Tien Chang; Hongzhong Zheng; Frank Mueller 001 (PDSW-DISCS@SC, 2017)

LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Kevin Hsieh; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (IEEE Comput. Archit. Lett., 2017)

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Nastaran Hajinazar; Kevin Hsieh; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (CoRR, 2017)

DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. - Mingyu Gao 001; Christina Delimitrou; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Christos Kozyrakis (IEEE Micro, 2017)

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. - Mu-Tien Chang; I. Stephen Choi; Dimin Niu; Hongzhong Zheng (ACM Great Lakes Symposium on VLSI, 2018)

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. - Shuangchen Li; Alvin Oliver Glova; Xing Hu 001; Peng Gu; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Yuan Xie 001 (MICRO, 2018)

CoNDA: efficient cache coherence support for near-data accelerators. - Amirali Boroumand; Saugata Ghose; Minesh Patel; Hasan Hassan; Brandon Lucia; Rachata Ausavarungnirun; Kevin Hsieh; Nastaran Hajinazar; Krishna T. Malladi; Hongzhong Zheng; Onur Mutlu (ISCA, 2019)

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. - Zhao Wang; Yijin Guan; Guangyu Sun 003; Dimin Niu; Yuhao Wang 002; Hongzhong Zheng; Yinhe Han 001 (ACA, 2020)

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. - Xinfeng Xie; Peng Gu; Yufei Ding 001; Dimin Niu; Hongzhong Zheng; Yuan Xie 001 (CoRR, 2021)

Area Efficient Pattern Representation of Binary Neural Networks on RRAM. - Feng Wang 046; Guojie Luo; Guang-Yu Sun 003; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (J. Comput. Sci. Technol., 2021)

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. - Peng Gu; Xinfeng Xie; Shuangchen Li; Dimin Niu; Hongzhong Zheng; Krishna T. Malladi; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. - Xingchen Li; Bingzhe Wu; Guangyu Sun 003; Zhe Zhang 006; Zhihang Yuan; Runsheng Wang; Ru Huang 001; Dimin Niu; Hongzhong Zheng; Zhichao Lu; Liang Zhao; Meng-Fan Marvin Chang; et al. (HPCA, 2022)

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Nianxiong Tan; Xiaopeng Yu 002; Hongzhong Zheng; Jianyi Meng; Xiaolang Yan; Yuan Xie 001 (ICPADS, 2022)

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. - Shuangchen Li; Dimin Niu; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Tianchan Guan; Yijin Guan; Heng Liu; Linyong Huang; Zhaoyang Du; Fei Xue; Yuanwei Fang; et al. (ISCA, 2022)

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. - Dimin Niu; Shuangchen Li; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Yijin Guan; Tianchan Guan; Fei Sun; Fei Xue; Lide Duan; Yuanwei Fang; Hongzhong Zheng; et al. (ISSCC, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Linyong Huang; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. - Linyong Huang; Zhe Zhang 006; Shuangchen Li; Dimin Niu; Yijin Guan; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

EPQuant: A Graph Neural Network compression approach based on product quantization. - Linyong Huang; Zhe Zhang 006; Zhaoyang Du; Shuangchen Li; Hongzhong Zheng; Yuan Xie 001; Nianxiong Tan (Neurocomputing, 2022)

Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. - Zhiyao Li; Jiaxiang Li; Taijie Chen; Dimin Niu; Hongzhong Zheng; Yuan Xie 001; Mingyu Gao 001 (ASPLOS (2), 2023)

Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (ICCAD, 2023)

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. - Chen Bai; Jiayi Huang 001; Xuechao Wei; Yuzhe Ma; Sicheng Li 001; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (MICRO, 2023)

TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. - Zheng Qu; Dimin Niu; Shuangchen Li; Hongzhong Zheng; Yuan Xie 001 (MICRO, 2023)

NPS: A Framework for Accurate Program Sampling Using Graph Neural Network. - Yuanwei Fang; Zihao Liu; Yanheng Lu; Jiawei Liu 004; Jiajie Li; Yi Jin; Jian Chen; Yen-Kuang Chen; Hongzhong Zheng; Yuan Xie 001 (CoRR, 2023)

MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing. - Xinfeng Xie; Peng Gu; Yufei Ding 001; Dimin Niu; Hongzhong Zheng; Yuan Xie 008 (ACM Trans. Archit. Code Optim., 2023)

Accelerating Distributed GNN Training by Codes. - Yanhong Wang; Tianchan Guan; Dimin Niu; Qiaosha Zou; Hongzhong Zheng; Chuanjin Richard Shi; Yuan Xie 001 (IEEE Trans. Parallel Distributed Syst., 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Tightly Coupled AI-ISP Vision Processor. - Hao Zhang 126; Sicheng Li 001; Yupeng Gui; Zhiyong Li 016; Shusong Xu; Yanheng Lu; Dimin Niu; Hongzhong Zheng; Yen-Kuang Chen; Yuan Xie 001; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2025)