A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiyan Sun; Qixiu Wu; Jiajie Tang; Zhihua Wang 001; Baoyong Chi (ESSCIRC, 2022)

IEEE ASSCC 2023/ Session 10/ Paper 10.5. - Ruichang Ma; Haikun Jia; Hongzhuo Liu; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2023)

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Baoyong Chi (CICC, 2023)

A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Baoyong Chi (ESSCIRC, 2023)

An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. - Qixiu Wu; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiwei Zhang; Zhihua Wang 001; Baoyong Chi (ISSCC, 2023)

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. - Angxiao Yan; Wei Deng 001; Haikun Jia; Shiyan Sun; Chao Tang; Bufan Zhu; Yu Fu; Hongzhuo Liu; Baoyong Chi (VLSI Technology and Circuits, 2023)

An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Baoyong Chi (CICC, 2024)

A Multireference PLL: Theory and Implementation. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. - Qixiu Wu; Wei Deng 001; Yaqian Sun; Haikun Jia; Hongzhuo Liu; Shiwei Zhang; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Baoyong Chi (CICC, 2025)

A Transformer-Based Series-Resonance CMOS VCO. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)

An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)