Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC. - Hooman Jarollahi; Richard F. Hobson (CDES, 2010)

Architecture and implementation of an associative memory using sparse clustered networks. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (ISCAS, 2012)

A low-power Content-Addressable Memory based on clustered-sparse networks. - Hooman Jarollahi; Vincent Gripon; Naoya Onizawa; Warren J. Gross (ASAP, 2013)

Selective decoding in associative memories based on Sparse-Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Warren J. Gross (GlobalSIP, 2013)

Reduced-complexity binary-weight-coded associative memories. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (ICASSP, 2013)

Associative Memories Based on Multiple-Valued Sparse Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross (ISMVL, 2014)

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Takahiro Hanyu; Warren J. Gross (SiPS, 2014)

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Noboru Sakimura; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (J. Signal Process. Syst., 2014)

Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. - Robin Danilo; Hooman Jarollahi; Vincent Gripon; Philippe Coussy; Laura Conde-Canencia; Warren J. Gross (ISCAS, 2015)

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. - Hooman Jarollahi; Vincent Gripon; Naoya Onizawa; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. - Naoya Onizawa; Hooman Jarollahi; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)