12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Giyong Yang; Hoonki Kim; Sanghoon Baek; Jonghoon Jung; Bongjae Kwon; Sungwee Cho; Hyuntaek Jung; Yongjae Choo; et al. (IEEE J. Solid State Circuits, 2017)

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. - Taejoong Song; Jonghoon Jung; Woojin Rim; Hoonki Kim; Yongho Kim; Changnam Park; Jeongho Do; Sunghyun Park 003; Sungwee Cho; Hyuntaek Jung; Bongjae Kwon; Hyun-Su Choi; et al. (ISSCC, 2018)

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. - Woong Choi; Jongsun Park 001; Hoonki Kim; Changnam Park; Taejoong Song (VLSI Circuits, 2018)

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{ mathrm{MIN}}$ Improvement and Energy Saving. - Hanwool Jeong; Se Hyeok Oh; Tae Woo Oh; Hoonki Kim; Changnam Park; Woojin Rim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. - Tae Hyun Kim; Hanwool Jeong; Juhyun Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Access, 2020)

24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Woojin Rim; Hoonki Kim; Keun Hwi Cho; Taeyeong Kim; Taejung Lee; Geumjong Bae; Dong-Won Kim; S. D. Kwon; Sanghoon Baek; Jonghoon Jung; Jongwook Kye; et al. (ISSCC, 2021)

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. - Hanwool Jeong; Tae Hyun Kim; Changnam Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Hoonki Kim; Woojin Rim; Hakchul Jung; Changnam Park; Inhak Lee; Sanghoon Baek; Jonghoon Jung (IEEE J. Solid State Circuits, 2022)

Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA. - Seungyoung Lee; Sungyup Jung; Yunkyeong Jang; Jungho Do; Jisu Yu; Hyeoungyu You; Minjae Jeong; Jinyoung Lim; Jiyun Han; Sangdo Park; Yongdeok Kim; Jooyeon Kwon; et al. (VLSI Technology and Circuits, 2023)

A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. - Tae-Hyun Kim; Juhyun Park; In Jun Jung; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)