On exponential fitting for circuit simulation. - Luís Miguel Silveira; Jacob K. White 001; Horácio C. Neto; Luís M. Vidigal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Bitwise Encoding of Finite State Machines. - José Monteiro 001; James H. Kukula; Srinivas Devadas; Horácio C. Neto (VLSI Design, 1994)

Towards an automatic path from JavaTM bytecodes to hardware through high-level synthesis. - João M. P. Cardoso; Horácio C. Neto (ICECS, 1998)

Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. - João M. P. Cardoso; Horácio C. Neto (FCCM, 1999)

On Applying Set Covering Models to Test Set Compaction. - Paulo F. Flores; Horácio C. Neto; João P. Marques Silva (Great Lakes Symposium on VLSI, 1999)

An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. - João M. P. Cardoso; Horácio C. Neto (VLSI, 1999)

Test pattern generation for width compression in BIST. - Paulo F. Flores; Horácio C. Neto; Krishnendu Chakrabarty; João Marques-Silva 001 (ISCAS (1), 1999)

Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. - Paulo F. Flores; José C. Costa; Horácio C. Neto; José Monteiro 001; João Marques-Silva 001 (VLSI Design, 1999)

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. - João M. P. Cardoso; Horácio C. Neto (FPL, 2001)

An exact solution to the minimum size test pattern problem. - Paulo F. Flores; Horácio C. Neto; João P. Marques Silva (ACM Trans. Design Autom. Electr. Syst., 2001)

System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. - Mário P. Véstias; Horácio C. Neto (IEEE International Workshop on Rapid System Prototyping, 2002)

DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. - Mário P. Véstias; Horácio C. Neto (SBCCI, 2003)

Compilation for FPGA-Based Reconfigurable Hardware. - João M. P. Cardoso; Horácio C. Neto (IEEE Des. Test Comput., 2003)

An Environment for Exploring Data-Driven Architectures. - Ricardo S. Ferreira 001; João M. P. Cardoso; Horácio C. Neto (FPL, 2004)

An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. - Pedro M. Domingos; Fernando M. Silva; Horácio C. Neto (FPL, 2005)

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. - Ricardo S. Ferreira 001; João M. P. Cardoso; Andre Toledo; Horácio C. Neto (SAMOS, 2005)

Area/Performance Improvement of NoC Architectures. - Mário P. Véstias; Horácio C. Neto (ARC, 2006)

Co-synthesis of a configurable SoC platform based on a network on chip architecture. - Mário P. Véstias; Horácio C. Neto (ASP-DAC, 2006)

On Reconfigurable Architectures for Efficient Matrix Inversion. - Goncalo M. de Matos; Horácio C. Neto (FPL, 2006)

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. - Mário P. Véstias; Horácio C. Neto (FPL, 2006)

Area and performance optimization of a generic network-on-chip architecture. - Mário P. Véstias; Horácio C. Neto (SBCCI, 2006)

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. - Mário P. Véstias; Horácio C. Neto (FPL, 2007)

Multiplier-based double precision floating point divider according to the IEEE-754 standard. - Vítor Silva; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (ARC, 2008)

Decimal multiplier on FPGA using embedded binary multipliers. - Horácio C. Neto; Mário P. Véstias (FPL, 2008)

Sorting Units for FPGA-Based Embedded Systems. - Rui Marcelino; Horácio C. Neto; João M. P. Cardoso (DIPES, 2008)

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (DSD, 2009)

Run-Time Reconfigurable Array Using Magnetic RAM. - Victor Silva 001; Luís Bica Oliveira; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (DSD, 2009)

Unbalanced FIFO sorting for FPGA-based systems. - Rui Marcelino; Horácio C. Neto; João M. P. Cardoso (ICECS, 2009)

Reconfigurable Circuits Using Magnetic Tunneling Junction Memories. - Victor Silva 001; Jorge R. Fernandes; Horácio C. Neto (DoCEIS, 2010)

Revisiting the Newton-Raphson Iterative Method for Decimal Division. - Mário P. Véstias; Horácio C. Neto (FPL, 2011)

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. - Mário P. Véstias; Horácio C. Neto (DSD, 2012)

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (DSD, 2012)

Sliding block Viterbi decoders in FPGA. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (FPL, 2012)

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. - Victor Silva 001; Mário P. Véstias; Horácio C. Neto; Jorge R. Fernandes (ICECS, 2012)

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. - Victor Silva 001; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (ReConFig, 2012)

Analysis of matrix multiplication on high density Virtex-7 FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2013)

A reconfigurable computing architecture using magnetic tunneling junction memories. - Victor Silva 001; Jorge R. Fernandes; Mário P. Véstias; Horácio C. Neto (FPL, 2013)

Design of a massively parallel computing architecture for dense matrix multiplication. - Wilson José; Ana Rita Silva; Mário P. Véstias; Horácio C. Neto (LASCAS, 2013)

Design of a multiband full-rate ultra-wideband receiver in FPGA. - Mário P. Véstias; Horácio C. Neto; Helena Sarmento (LASCAS, 2013)

Very low resource table-based FPGA evaluation of elementary functions. - Horácio C. Neto; Mário P. Véstias (ReConFig, 2013)

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. - Wilson José; Ana Rita Silva; Horácio C. Neto; Mário P. Véstias (FPL, 2014)

Trends of CPU, GPU and FPGA for high-performance computing. - Mário P. Véstias; Horácio C. Neto (FPL, 2014)

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. - Mário P. Véstias; Horácio C. Neto (CoRR, 2014)

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. - João Pinhão; Wilson José; Horácio C. Neto; Mário P. Véstias (DSD, 2015)

Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions. - Victor M. Goncalves Martins; Joao Gabriel Reis; Horácio C. Neto; Eduardo Augusto Bezerra (FCCM, 2015)

Enhancing stochastic computations via process variation. - Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (FPL, 2015)

A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow. - Victor M. Goncalves Martins; Paulo Ricardo Cechelero Villa; Horácio C. Neto; Eduardo Augusto Bezerra (ISVLSI, 2015)

FPGA redundancy recovery based on partial bitstreams for multiple partitions. - Victor M. Goncalves Martins; Joao Gabriel Reis; Horácio C. Neto; Eduardo Augusto Bezerra (LATS, 2015)

Designing Hardware/Software Systems for Embedded High-Performance Computing. - Mário P. Véstias; Rui Policarpo Duarte; Horácio C. Neto (CoRR, 2015)

Multi-core for K-means clustering on FPGA. - Jose Canilho; Mário P. Véstias; Horácio C. Neto (FPL, 2016)

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (ICRC, 2016)

K-means clustering on CGRA. - João D. Lopes; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (FPL, 2017)

Parallel dot-products for deep learning on FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2017)

Decimal addition on FPGA based on a mixed BCD/excess-6 representation. - Horácio C. Neto; Mário P. Véstias (Microprocess. Microsystems, 2017)

Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems. - Rui Policarpo Duarte; Horácio C. Neto (DSC, 2018)

An Efficient Exact Fused Dot Product Processor in FPGA. - Luís Fiolhais; Horácio C. Neto (FPL, 2018)

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2018)

FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering. - Rui Policarpo Duarte; Álvaro Simões; Rui Henriques; Horácio C. Neto (PBio@EuroMPI, 2018)

Improving the area of fast parallel decimal multipliers. - Mário P. Véstias; Horácio C. Neto (Microprocess. Microsystems, 2018)

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. - Helena Cruz; Rui Policarpo Duarte; Horácio C. Neto (ARC, 2019)

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2019)

kNN-STUFF: kNN STreaming Unit for Fpgas. - João Vieira; Rui Policarpo Duarte; Horácio C. Neto (IEEE Access, 2019)

Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection. - Helena Cruz; Rui Policarpo Duarte; Horácio C. Neto (J. Aerosp. Inf. Syst., 2019)

Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. - Rui Policarpo Duarte; Helena Cruz; Horácio C. Neto (ARC, 2020)

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (IEEE Access, 2020)

Moving Deep Learning to the Edge. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Algorithms, 2020)

A fast and scalable architecture to run convolutional neural networks in low density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Microprocess. Microsystems, 2020)

A Full Featured Configurable Accelerator for Object Detection With YOLO. - Daniel Pestana; Pedro R. Miranda; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (IEEE Access, 2021)

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. - Mário P. Véstias; Horácio C. Neto (Algorithms, 2021)

Configurable Hardware Core for IoT Object Detection. - Pedro R. Miranda; Daniel Pestana; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (Future Internet, 2021)

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. - Helena Cruz; Mário P. Véstias; José Monteiro 001; Horácio C. Neto; Rui Policarpo Duarte (Remote. Sens., 2022)

System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics. - Francisco Melo; Horácio C. Neto; Hugo Plácido da Silva (Sensors, 2022)

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. - David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022)

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. - Maria Inês Frutuoso; Horácio C. Neto; Mário P. Véstias; Rui Policarpo Duarte (Algorithms, 2023)

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2023)

LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. - Henrique B. Brum; Mário P. Véstias; Horácio C. Neto (ARC, 2024)

PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. - José T. de Sousa; João D. Lopes; Micaela Serôdio; Horácio C. Neto; Mário P. Véstias (ARITH, 2024)

Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. - Miguel Reis; Mário P. Véstias; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2024)

Coarse-Grained Reconfigurable Arrays for High-Performance Low-Power Deep Neural Networks on Embedded Devices. - João D. Lopes; Horácio C. Neto; José T. de Sousa (DoCEIS, 2025)