Design and VLSI Implementation of a Unified Synapse-Neuron Architecture. - Hormoz Djahanshahi; Majid Ahmadi; Graham A. Jullien; William C. Miller (Great Lakes Symposium on VLSI, 1996)

A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor. - Hormoz Djahanshahi; Majid Ahmadi; Graham A. Jullien; William C. Miller (ICNN, 1996)

High-speed ECL-compatible serial I/O in 0.35 μm CMOS. - Hormoz Djahanshahi; Flemming Hansen; C. André T. Salama (ICECS, 1998)

A Low-Variation Nonlinear Neuron Circuit. - Hormoz Djahanshahi; Majid Ahmadi; Graham A. Jullien; William C. Miller (J. Circuits Syst. Comput., 1998)

Neural Network Integrated Circuits with Single-Block Mixed Signal Arrays. - Hormoz Djahanshahi; Majid Ahmadi; Graham A. Jullien; William C. Miller (J. Circuits Syst. Comput., 1998)

Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling. - Hormoz Djahanshahi; Flemming Hansen; C. André T. Salama (CICC, 1999)

Sensitivity study and improvements on a nonlinear resistive-type neuron circuit. - Hormoz Djahanshahi; Majid Ahmadi; Graham A. Jullien; William C. Miller (ICECS, 1999)

Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications. - Hormoz Djahanshahi; C. André T. Salama (ISCAS (2), 1999)

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS. - Hormoz Djahanshahi; Flemming Hansen; C. André T. Salama (IEEE J. Solid State Circuits, 1999)

Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications. - Hormoz Djahanshahi; C. André T. Salama (IEEE J. Solid State Circuits, 2000)

Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO. - Pedram Sameni; Chris Siu; Shahriar Mirabbasi; Hormoz Djahanshahi; Marwa Hamour; Krzysztof Iniewski; Jatinder Chana (ISCAS (5), 2005)

Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers. - Pedram Sameni; Chris Siu; Shahriar Mirabbasi; Hormoz Djahanshahi; Marwa Hamour; Krzysztof Iniewski; Jatinder Chana (EURASIP J. Wirel. Commun. Netw., 2006)

A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS. - Reza Molavi; Shahriar Mirabbasi; Hormoz Djahanshahi (ISCAS, 2011)

Design and verification of integrated inductors in CMOS. - Reza Molavi; Shahriar Mirabbasi; Hormoz Djahanshahi (CCECE, 2012)

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration. - Reza Molavi; Hormoz Djahanshahi; Rod Zavari; Shahriar Mirabbasi (J. Electr. Comput. Eng., 2013)

On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise. - Amir Hossein Masnadi Shirazi; Amir Nikpaik; Reza Molavi; Sam Lightbody; Hormoz Djahanshahi; Mazhareddin Taghivand; Shahriar Mirabbasi; Sudip Shekhar (IEEE J. Solid State Circuits, 2016)

A Hardened-By-Design Technique for LC-Tank Voltage Controlled Oscillator. - Zhichao Zhang; Li Chen 001; Hormoz Djahanshahi (CCECE, 2018)

A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS. - Zhichao Zhang; Li Chen 001; Hormoz Djahanshahi (CCECE, 2018)

On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators. - Milad Haghi Kashani; Reza Molavi; Hormoz Djahanshahi; Shahriar Mirabbasi (ISCAS, 2018)

A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz. - Amir Hossein Masnadi Shirazi; Mohammad Mahani; Hossein Miri Lavasani; Shahriar Mirabbasi; Sudip Shekhar; Rod Zavari; Hormoz Djahanshahi (CICC, 2020)

A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20-28GHz LCVCO and a 51-62GHz Self-Mixing LCVCO. - Omid Esmaeeli; Sam Lightbody; Amir Hossein Masnadi Shirazi; Hormoz Djahanshahi; Rod Zavari; Shahriar Mirabbasi; Sudip Shekhar (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)