Statistical Timing Analysis of Combinational Circuits. - Srinivas Devadas; Horng-Fei Jyu; Kurt Keutzer; Sharad Malik (ICCD, 1992)

Statistical Timing Optimization of Combinatorial Logic Circuits. - Horng-Fei Jyu; Sharad Malik (ICCD, 1993)

Statistical timing analysis of combinational logic circuits. - Horng-Fei Jyu; Sharad Malik; Srinivas Devadas; Kurt Keutzer (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Statistical Delay Modeling in Logic Design and Synthesis. - Horng-Fei Jyu; Sharad Malik (DAC, 1994)

Prediction of interconnect delay in logic synthesis. - Horng-Fei Jyu; Sharad Malik (ED&TC, 1995)