On-chip electrostatic discharge ESD. - Horst A. Gieser (Microelectron. Reliab., 2003)

Transient latch-up: experimental analysis and device simulation. - S. Bargstädt-Franke; Wolfgang Stadler; Kai Esmark; Martin Streibl; Krzysztof Domanski; Horst A. Gieser; Heinrich Wolf; Waclaw Bala (Microelectron. Reliab., 2005)

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits. - Heinrich Wolf; Horst A. Gieser; Wolfgang Soldner; Harald Gossner (Microelectron. Reliab., 2005)

Capacitively coupled transmission line pulsing cc-TLP–a traceable and reproducible stress method in the CDM-domain. - Heinrich Wolf; Horst A. Gieser; Wolfgang Stadler; Wolfgang Wilkening (Microelectron. Reliab., 2005)

Transient-induced latch-up test setup for wafer-level and package-level. - Detlef Bonfert; Horst A. Gieser; Heinrich Wolf; M. Frank; A. Konrad; J. Schulz (Microelectron. Reliab., 2006)

Study of CDM specific effects for a smart power input protection structure. - M. Etherton; Ning Qu; J. Willemen; Wolfgang Wilkening; S. Mettler; Mariano Dissegna; R. Stella; L. Zullino; A. Andreini; Horst A. Gieser (Microelectron. Reliab., 2006)

ESD Susceptibility of Submicron Air Gaps. - Heinrich Wolf; Horst A. Gieser; Detlef Bonfert; Markus Hauser (Microelectron. Reliab., 2006)

Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP. - Heinrich Wolf; Horst A. Gieser; Dirk Walter (Microelectron. Reliab., 2009)

Electrostatic discharge sensitivity investigation on organic field-effect thin film transistors. - Tekfouy Lim; Horst A. Gieser; Luca Santarelli; Franco Cacialli (NEWCAS, 2015)

Integrated flow for reverse engineering of nanoscale technologies. - Bernhard Lippmann; Michael Werner; Niklas Unverricht; Aayush Singla; Peter Egger; Anja Dübotzky; Horst A. Gieser; Martin Rasche; Oliver Kellermann; Helmut Graeb (ASP-DAC, 2019)

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. - Bernhard Lippmann; Niklas Unverricht; Aayush Singla; Matthias Ludwig 005; Michael Werner; Peter Egger; Anja Dübotzky; Helmut Gräb; Horst A. Gieser; Martin Rasche; Oliver Kellermann (Integr., 2020)

Investigating Profiled Side-Channel Attacks Against the DES Key Schedule. - Johann Heyszl; Katja Miller; Florian Unterstein; Marc Schink; Alexander Wagner; Horst A. Gieser; Sven Freud; Tobias Damm; Dominik Klein 001; Dennis Kügler (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. - Bernhard Lippmann; Ann-Christin Bette; Matthias Ludwig 005; Johannes Mutter; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser; Nicola Kovac; Tobias Zweifel; Martin Rasche; Oliver Kellermann (DATE, 2022)

Analysis of Piezoresistive Silicon as Sense Element for use in Flexible Tactile Sensors. - Vartika Verma; Eslam Ahmed; Nicola Kovac; Christof Landesberger; Horst A. Gieser; Ralf Brederlow (IEEE SENSORS, 2024)

Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC). - Bernhard Lippmann; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser (DATE, 2025)