Clock cycle estimation based on dead time and control unit area minimization. - Hortensia Mecha; Milagros Fernández; Román Hermida; Daniel Mozos; Katzalin Olcoz (Microprocess. Microprogramming, 1994)

A method for area estimation of data-path in high level synthesis. - Hortensia Mecha; Milagros Fernández; Francisco Tirado; Julio Septién; D. Motes; Katzalin Olcoz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Interconnection Delay and Clock Cycle Selection in High Level Synthesis. - Hortensia Mecha; Milagros Fernández (VLSI Design, 1997)

A unified approach for scheduling and allocation. - R. Moreno; Román Hermida; Milagros Fernández; Hortensia Mecha (Integr., 1997)

A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. - Juan Antonio Maestro; Daniel Mozos; Hortensia Mecha (DATE, 1998)

Unified data path allocation and BIST intrusion. - Katzalin Olcoz; Francisco Tirado; Hortensia Mecha (Integr., 1999)

A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. - Javier Resano; Daniel Mozos; Elena Pérez-Miñana; Hortensia Mecha; Julio Septién (PATMOS, 2003)

Analyzing communication overheads during hardware/software partitioning. - Javier Resano; M. Elena Pérez; Daniel Mozos; Hortensia Mecha; Julio Septién (Microelectron. J., 2003)

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. - Jesús Tabero; Julio Septién; Hortensia Mecha; Daniel Mozos (FPL, 2004)

Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. - Sara Román Navarro; Julio Septién; Hortensia Mecha; Daniel Mozos (ARC, 2006)

Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. - Jesús Tabero; Julio Septién; Hortensia Mecha; Daniel Mozos (ASP-DAC, 2006)

Partition Based Dynamic 2D HW Multitasking Management. - Sara Román Navarro; Hortensia Mecha; Daniel Mozos; Julio Septién (DSD, 2006)

2D defragmentation heuristics for hardware multitasking on reconfigurable devices. - Julio Septién; Hortensia Mecha; Daniel Mozos; Jesús Tabero (IPDPS, 2006)

Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. - Angel Luis González Bravo; Hortensia Mecha; Julio Septién; Sara Román Navarro; Daniel Mozos (ERSA, 2008)

FPGA Resource Management Using Internal RAM as Aata Cache. - Laura Sánchez; Julio Septién; Daniel Mozos; Hortensia Mecha; Angel Luis González Bravo (ERSA, 2008)

Resource Management for Hw Multitasking in Three Dimensional FPGAs. - Jose Antonio Valero; Julio Septién; Daniel Mozos; Hortensia Mecha; Angel Luis González Bravo (ERSA, 2008)

Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. - Julio Septién; Daniel Mozos; Hortensia Mecha; Jesús Tabero; Miguel Angel García de Dios (IPDPS, 2008)

Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays. - S. Roman; Hortensia Mecha; Daniel Mozos; Julio Septién (IET Comput. Digit. Tech., 2008)

Allocation heuristics and defragmentation measures for reconfigurable systems management. - Jesús Tabero; Julio Septién; Hortensia Mecha; Daniel Mozos (Integr., 2008)

3D FPGA resource management and fragmentation metric for hardware multitasking. - Jose Antonio Valero; Julio Septién; Daniel Mozos; Hortensia Mecha (IPDPS, 2009)

A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles. - Sara Román Navarro; Hortensia Mecha; Daniel Mozos (ERSA, 2010)

Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA. - Marcos Sánchez-Élez; Inmaculada Pardines; Felipe Serrano 002; Hortensia Mecha (DATE, 2016)

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs. - Juan Antonio Clemente; Wassim Mansour; Rafic Ayoubi; Felipe Serrano 002; Hortensia Mecha; Haissam Ziade; Wassim El Falou; Raoul Velazco (Neurocomputing, 2016)

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. - Javier Olivito; Felipe Serrano 002; Juan Antonio Clemente; Hortensia Mecha; Javier Resano (IET Comput. Digit. Tech., 2018)

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. - Adrián Alcolea Morena; Javier Olivito; Javier Resano; Hortensia Mecha (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles. - Juan Carlos Fabero; Golnaz Korkian; Francisco J. Franco; Hortensia Mecha; Manon Letiche; Juan Antonio Clemente (LATS, 2021)

Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs. - Mohammadreza Rezaei; Francisco J. Franco; Juan Carlos Fabero; Hortensia Mecha; Helmut Puchner; Juan Antonio Clemente (LATS, 2021)

Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories. - Golnaz Korkian; Daniel León; Francisco J. Franco; Juan Carlos Fabero; Manon Letiche; Yolanda Morilla; Pedro Martín-Holgado; Helmut Puchner; Hortensia Mecha; Juan Antonio Clemente (IEEE Access, 2022)

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles. - Juan Carlos Fabero; Golnaz Korkian; Francisco J. Franco; Guillaume Hubert; Hortensia Mecha; Manon Letiche; Juan Antonio Clemente (Microprocess. Microsystems, 2023)