Fast Prototyping with Co-operation of Simulation and Emulation. - Siavash Bayat Sarmadi; Seyed Ghassem Miremadi; Ghazanfar Asadi; Ali Reza Ejlali (FPL, 2002)

Speedup analysis in simulation-emulation co-operation. - Seyed Ghassem Miremadi; Siavash Bayat Sarmadi; Ghazanfar Asadi (FPT, 2002)

A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. - Ali Reza Ejlali; Seyed Ghassem Miremadi; Hamid R. Zarandi; Ghazanfar Asadi; Siavash Bayat Sarmadi (DSN, 2003)

Fault injection into SRAM-based FPGAs for the analysis of SEU effects. - Ghazanfar Asadi; Seyed Ghassem Miremadi; Hamid R. Zarandi; Alireza Ejlali (FPT, 2003)

Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. - Ghazanfar Asadi; Seyed Ghassem Miremadi; Hamid R. Zarandi; Ali Reza Ejlali (PRDC, 2004)

An Accurate SER Estimation Method Based on Propagation Probability. - Ghazanfar Asadi; Mehdi Baradaran Tahoori (DATE, 2005)

Soft Error Modeling and Protection for Sequential Elements. - Hossein Asadi 001; Mehdi Baradaran Tahoori (DFT, 2005)

Soft error rate estimation and mitigation for SRAM-based FPGAs. - Ghazanfar Asadi; Mehdi Baradaran Tahoori (FPGA, 2005)

An analytical approach for soft error rate estimation in digital circuits. - Ghazanfar Asadi; Mehdi Baradaran Tahoori (ISCAS (3), 2005)

Balancing Performance and Reliability in the Memory Hierarchy. - Hossein Asadi 001; Vilas Sridharan; Mehdi Baradaran Tahoori; David R. Kaeli (ISPASS, 2005)

Soft Error Mitigation for SRAM-Based FPGAs. - Ghazanfar Asadi; Mehdi Baradaran Tahoori (VTS, 2005)

Vulnerability analysis of L2 cache elements to single event upsets. - Hossein Asadi 001; Vilas Sridharan; Mehdi Baradaran Tahoori; David R. Kaeli (DATE, 2006)

Soft error derating computation in sequential circuits. - Hossein Asadi 001; Mehdi Baradaran Tahoori (ICCAD, 2006)

Soft error hardening for logic-level designs. - Hossein Asadi 001; Mehdi Baradaran Tahoori (ISCAS, 2006)

Reducing Data Cache Susceptibility to Soft Errors. - Vilas Sridharan; Hossein Asadi 001; Mehdi Baradaran Tahoori; David R. Kaeli (IEEE Trans. Dependable Secur. Comput., 2006)

Estimating Error Propagation Probabilities with Bounded Variances. - Hossein Asadi 001; Mehdi Baradaran Tahoori; Chandra Tirumurti (DFT, 2007)

Case Study: Soft Error Rate Analysis in Storage Systems. - Brian Mullins; Hossein Asadi 001; Mehdi Baradaran Tahoori; David R. Kaeli; Kevin Granlund; Rudy Bauer; Scott Romano (VTS, 2007)

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. - Hossein Asadi 001; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Obtaining FPGA soft error rate in high performance information systems. - Mehdi Baradaran Tahoori; Hossein Asadi 001; Brian Mullins; David R. Kaeli (Microelectron. Reliab., 2009)

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. - Mahdi Fazeli; Seyed Ghassem Miremadi; Hossein Asadi 001; Mehdi Baradaran Tahoori (DSD, 2010)

A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. - Mahdi Fazeli; Seyed Ghassem Miremadi; Hossein Asadi 001; Seyed Nematollah Ahmadian (DSN, 2010)

System-Level Vulnerability Estimation for Data Caches. - Alireza Haghdoost 001; Hossein Asadi 001; Amirali Baniasadi (PRDC, 2010)

Soft error modeling and remediation techniques in ASIC designs. - Hossein Asadi 001; Mehdi Baradaran Tahoori (Microelectron. J., 2010)

ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. - Mojtaba Ebrahimi; Seyed Ghassem Miremadi; Hossein Asadi 001 (DATE, 2011)

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). - Mahdi Fazeli; Seyed Nematollah Ahmadian; Seyed Ghassem Miremadi; Hossein Asadi 001; Mehdi Baradaran Tahoori (DATE, 2011)

Efficient algorithms to accurately compute derating factors of digital circuits. - Hossein Asadi 001; Mehdi Baradaran Tahoori; Mahdi Fazeli; Seyed Ghassem Miremadi (Microelectron. Reliab., 2012)

FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. - Mohammad Hossein Hajkazemi; Amirali Baniasadi; Hossein Asadi 001 (ASAP, 2013)

CLASS: Combined logic and architectural soft error sensitivity analysis. - Mojtaba Ebrahimi; Liang Chen 014; Hossein Asadi 001; Mehdi Baradaran Tahoori (ASP-DAC, 2013)

A layout-based approach for multiple event transient analysis. - Mojtaba Ebrahimi; Hossein Asadi 001; Mehdi Baradaran Tahoori (DAC, 2013)

FTSPM: A Fault-Tolerant ScratchPad Memory. - Amir Mahdi Hosseini Monazzah; Hamed Farbeh; Seyed Ghassem Miremadi; Mahdi Fazeli; Hossein Asadi 001 (DSN, 2013)

Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. - Mojtaba Ebrahimi; Seyed Ghassem Miremadi; Hossein Asadi 001; Mahdi Fazeli (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A power-efficient reconfigurable architecture using PCM configuration technology. - Ali Ahari; Hossein Asadi 001; Behnam Khaleghi; Mehdi Baradaran Tahoori (DATE, 2014)

Towards dark silicon era in FPGAs using complementary hard logic design. - Ali Ahari; Behnam Khaleghi; Zahra Ebrahimi; Hossein Asadi 001; Mehdi Baradaran Tahoori (FPL, 2014)

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. - Ali Ahari; Hossein Asadi 001; Mehdi Baradaran Tahoori (ReCoSoC, 2014)

CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors. - Hossein Asadi 001; Alireza Haghdoost 001; Morteza Ramezani; Nima Elyasi; Amirali Baniasadi (Microelectron. Reliab., 2014)

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. - Siavash Rezaei; Seyed Ghassem Miremadi; Hossein Asadi 001; Mahdi Fazeli (Microelectron. Reliab., 2014)

Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. - Sadegh Yazdanshenas; Hossein Asadi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An efficient reconfigurable architecture by characterizing most frequent logic functions. - Iman Ahmadpour; Behnam Khaleghi; Hossein Asadi 001 (FPL, 2015)

DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling. - Mojtaba Tarihi; Hossein Asadi 001; Hamid Sarbazi-Azad (SIGMETRICS, 2015)

FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. - Behnam Khaleghi; Ali Ahari; Hossein Asadi 001; Siavash Bayat Sarmadi (IEEE Embed. Syst. Lett., 2015)

On endurance and performance of erasure codes in SSD-based storage systems. - Saeideh Alinezhad Chamazcoti; Ziba Delavari; Seyed Ghassem Miremadi; Hossein Asadi 001 (Microelectron. Reliab., 2015)

Operating system level data tiering using online workload characterization. - Reza Salkhordeh; Hossein Asadi 001; Shahriar Ebrahimi (J. Supercomput., 2015)

A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. - Sadegh Yazdanshenas; Hossein Asadi 001; Behnam Khaleghi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. - Reza Salkhordeh; Hossein Asadi 001 (DATE, 2016)

Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. - Behnam Khaleghi; Behzad Omidi; Hussam Amrouch; Jörg Henkel; Hossein Asadi 001 (FPL, 2016)

Introduction: Special Section on Architecture of Future Many Core Systems. - Hossein Asadi 001; Paolo Ienne; Hamid Sarbazi-Azad (Microprocess. Microsystems, 2016)

Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. - Hossein Asadi 001; Paolo Ienne; Hamid Sarbazi-Azad (IEEE Trans. Computers, 2016)

A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization. - Mojtaba Tarihi; Hossein Asadi 001; Alireza Haghdoost 001; Mohammad Arjomand; Hamid Sarbazi-Azad (IEEE Trans. Computers, 2016)

Layout-Based Modeling and Mitigation of Multiple Event Transients. - Mojtaba Ebrahimi; Hossein Asadi 001; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. - Hamed Farbeh; Nooshin Sadat Mirzadeh; Nahid Farhady Ghalaty; Seyed Ghassem Miremadi; Mahdi Fazeli; Hossein Asadi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. - Sadegh Yazdanshenas; Behnam Khaleghi; Paolo Ienne; Hossein Asadi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Evaluating impact of human errors on the availability of data storage systems. - Mostafa Kishani; Reza Eftekhari; Hossein Asadi 001 (DATE, 2017)

A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. - Zeinab Seifoori; Behnam Khaleghi; Hossein Asadi 001 (DATE, 2017)

PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era. - Zahra Ebrahimi; Behnam Khaleghi; Hossein Asadi 001 (IEEE Trans. Computers, 2017)

Investigating power outage effects on reliability of solid-state drives. - Saba Ahmadian; Farhad Taheri; Mehrshad Lotfi; Maryam Karimi; Hossein Asadi 001 (DATE, 2018)

Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era. - Zeinab Seifoori; Zahra Ebrahimi; Behnam Khaleghi; Hossein Asadi 001 (Adv. Comput., 2018)

ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. - Saba Ahmadian; Onur Mutlu; Hossein Asadi 001 (Proc. ACM Meas. Anal. Comput. Syst., 2018)

A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry. - Behnam Khaleghi; Hossein Asadi 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. - Reza Salkhordeh; Shahriar Ebrahimi; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. - Mostafa Kishani; Hossein Asadi 001 (IEEE Trans. Reliab., 2018)

ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (ASP-DAC, 2019)

LBICA: A Load Balancer for I/O Cache Architectures. - Saba Ahmadian; Reza Salkhordeh; Hossein Asadi 001 (DATE, 2019)

Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (DATE, 2019)

A Machine Learning Approach for Power Gating the FPGA Routing Network. - Zeinab Seifoori; Hossein Asadi 001; Mirjana Stojilovic (FPT, 2019)

A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. - Omid Ranjbar; Siavash Bayat Sarmadi; Fatemeh Pooyan; Hossein Asadi 001 (J. Electron. Test., 2019)

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. - Elham Cheshmikhani; Hamed Farbeh; Seyed Ghassem Miremadi; Hossein Asadi 001 (IEEE Trans. Computers, 2019)

An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. - Reza Salkhordeh; Onur Mutlu; Hossein Asadi 001 (IEEE Trans. Computers, 2019)

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. - Sajjad Tamimi; Zahra Ebrahimi; Behnam Khaleghi; Hossein Asadi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. - Reza Salkhordeh; Mostafa Hadizadeh; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2019)

Dependability Analysis of Data Storage Systems in Presence of Soft Errors. - Mostafa Kishani; Mehdi Baradaran Tahoori; Hossein Asadi 001 (IEEE Trans. Reliab., 2019)

Estimating and Mitigating Aging Effects in Routing Network of FPGAs. - Behnam Khaleghi; Behzad Omidi; Hussam Amrouch; Jörg Henkel; Hossein Asadi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. - Mostafa Hadizadeh; Elham Cheshmikhani; Hossein Asadi 001 (DATE, 2020)

A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. - Mostafa Kishani; Saba Ahmadian; Hossein Asadi 001 (IEEE Trans. Computers, 2020)

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (IEEE Trans. Reliab., 2020)

PADSA: Priority-Aware Block Data Storage Architecture for Edge Cloud Serving Autonomous Vehicles. - Mostafa Kishani; Zdenek Becvar; Hossein Asadi 001 (VNC, 2021)

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. - Zeinab Seifoori; Hossein Asadi 001; Mirjana Stojilovic (IEEE Access, 2021)

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. - Saba Ahmadian; Farhad Taheri; Hossein Asadi 001 (IEEE Trans. Emerg. Top. Comput., 2021)

ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. - Saba Ahmadian; Reza Salkhordeh; Onur Mutlu; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2021)

Reducing Storage and Communication Latencies in Vehicular Edge Cloud. - Mostafa Kishani; Zdenek Becvar; Mohammadsaleh Nikooroo; Hossein Asadi 001 (EuCNC, 2022)

An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. - Mohammadamin Ajdari; Patrick Raaf; Mostafa Kishani; Reza Salkhordeh; Hossein Asadi 001; André Brinkmann (Proc. ACM Meas. Anal. Comput. Syst., 2022)

3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. - Elham Cheshmikhani; Hamed Farbeh; Hossein Asadi 001 (IEEE Trans. Computers, 2022)

RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. - Shahriar Ebrahimi; Reza Salkhordeh; Seyed Ali Osia; Ali Taheri; Hamid R. Rabiee; Hossein Asadi 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Quick Generation of SSD Performance Models Using Machine Learning. - Mojtaba Tarihi; Soheil Azadvar; Arash Tavakkol; Hossein Asadi 001; Hamid Sarbazi-Azad (IEEE Trans. Emerg. Top. Comput., 2022)

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. - Mostafa Hadizadeh; Elham Cheshmikhani; Maysam Rahmanpour; Onur Mutlu; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2022)

Re-architecting I/O Caches for Emerging Fast Storage Devices. - Mohammadamin Ajdari; Pouria Peykani Sani; Amirhossein Moradi; Masoud Khanalizadeh Imani; Amir Hossein Bazkhanei; Hossein Asadi 001 (ASPLOS (3), 2023)

PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era. - Zeinab Seifoori; Behzad Omidi; Hossein Asadi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers. - Eric Borba; Reza Salkhordeh; Salim Mimouni; Eduardo Tavares; Paulo Maciel 001; Hossein Asadi 001; André Brinkmann (ARCS, 2024)

Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems. - Mohammadamin Ajdari; Behrang Montazerzohour; Kimia Abdi; Hossein Asadi 001 (IEEE Comput. Archit. Lett., 2024)

Skip TLB flushes for reused pages within mmap's. - Frederic Schimmelpfennig; André Brinkmann; Hossein Asadi 001; Reza Salkhordeh (CoRR, 2024)

Joint Optimization of Communication and Storage Latencies for Vehicular Edge Computing. - Mostafa Kishani; Zdenek Becvar; Mohammadsaleh Nikooroo; Hossein Asadi 001 (IEEE Trans. Intell. Transp. Syst., 2024)

From SSDs Back to HDDs: Optimizing VDO to Support Inline Deduplication and Compression for HDDs as Primary Storage Media. - Patrick Raaf; André Brinkmann; Eric Borba; Hossein Asadi 001; Sai Narasimhamurthy; John Bent; Mohamad El-Batal; Reza Salkhordeh (ACM Trans. Storage, 2024)

No Time to Halt: In-Situ Analysis for Large-Scale Data Processing via Virtual Snapshotting. - Reza Salkhordeh; Felix Martin Schuhknecht; Hossein Asadi 001; Steffen Eiden; André Brinkmann (EDBT, 2025)

Enhancing mmap scalability by saving TLB shootdowns during page recycling. - Frederic Schimmelpfennig; André Brinkmann; Hossein Asadi 001; Reza Salkhordeh (PDP, 2025)

ELICA: Efficient and Load Balanced I/O Cache Architecture for Hyperconverged Infrastructures. - Mostafa Kishani; Sina Ahmadi; Saba Ahmadian; Reza Salkhordeh; Zdenek Becvar; Onur Mutlu; André Brinkmann; Hossein Asadi 001 (IEEE Trans. Parallel Distributed Syst., 2025)