Hossein Asadi

Orcid: 0000-0002-0264-3865

Affiliations:
  • Sharif University of Technology, Tehran, Iran


According to our database1, Hossein Asadi authored at least 86 papers between 2002 and 2023.

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Bibliography

2023
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Re-architecting I/O Caches for Emerging Fast Storage Devices.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers.
IEEE Trans. Parallel Distributed Syst., 2022

Quick Generation of SSD Performance Models Using Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022

RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2022

3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison.
IEEE Trans. Computers, 2022

An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems.
Proc. ACM Meas. Anal. Comput. Syst., 2022

Reducing Storage and Communication Latencies in Vehicular Edge Cloud.
Proceedings of the 2022 Joint European Conference on Networks and Communications & 6G Summit, 2022

2021
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms.
IEEE Trans. Parallel Distributed Syst., 2021

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems.
IEEE Trans. Emerg. Top. Comput., 2021

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing.
IEEE Access, 2021

PADSA: Priority-Aware Block Data Storage Architecture for Edge Cloud Serving Autonomous Vehicles.
Proceedings of the 13th IEEE Vehicular Networking Conference, 2021

2020
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches.
IEEE Trans. Reliab., 2020

A Modeling Framework for Reliability of Erasure Codes in SSD Arrays.
IEEE Trans. Computers, 2020

STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Estimating and Mitigating Aging Effects in Routing Network of FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Dependability Analysis of Data Storage Systems in Presence of Soft Errors.
IEEE Trans. Reliab., 2019

An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs.
IEEE Trans. Parallel Distributed Syst., 2019

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories.
IEEE Trans. Computers, 2019

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches.
IEEE Trans. Computers, 2019

A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs.
J. Electron. Test., 2019

A Machine Learning Approach for Power Gating the FPGA Routing Network.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LBICA: A Load Balancer for I/O Cache Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems.
IEEE Trans. Reliab., 2018

ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization.
IEEE Trans. Parallel Distributed Syst., 2018

A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms.
Proc. ACM Meas. Anal. Comput. Syst., 2018

Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era.
Adv. Comput., 2018

Investigating power outage effects on reliability of solid-state drives.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era.
IEEE Trans. Computers, 2017

A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Evaluating impact of human errors on the availability of data storage systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Layout-Based Modeling and Mitigation of Multiple Event Transients.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization.
IEEE Trans. Computers, 2016

Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems.
IEEE Trans. Computers, 2016

Introduction: Special Section on Architecture of Future Many Core Systems.
Microprocess. Microsystems, 2016

Stress-aware routing to mitigate aging effects in SRAM-based FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Operating system level data tiering using online workload characterization.
J. Supercomput., 2015

On endurance and performance of erasure codes in SSD-based storage systems.
Microelectron. Reliab., 2015

FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic.
IEEE Embed. Syst. Lett., 2015

DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling.
Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015

An efficient reconfigurable architecture by characterizing most frequent logic functions.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates.
Microelectron. Reliab., 2014

CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors.
Microelectron. Reliab., 2014

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Towards dark silicon era in FPGAs using complementary hard logic design.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A power-efficient reconfigurable architecture using PCM configuration technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

FTSPM: A Fault-Tolerant ScratchPad Memory.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

A layout-based approach for multiple event transient analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

CLASS: Combined logic and architectural soft error sensitivity analysis.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Efficient algorithms to accurately compute derating factors of digital circuits.
Microelectron. Reliab., 2012

2011
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).
Proceedings of the Design, Automation and Test in Europe, 2011

ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Soft error modeling and remediation techniques in ASIC designs.
Microelectron. J., 2010

System-Level Vulnerability Estimation for Data Caches.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Obtaining FPGA soft error rate in high performance information systems.
Microelectron. Reliab., 2009

2007
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Case Study: Soft Error Rate Analysis in Storage Systems.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Estimating Error Propagation Probabilities with Bounded Variances.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Reducing Data Cache Susceptibility to Soft Errors.
IEEE Trans. Dependable Secur. Comput., 2006

Soft error hardening for logic-level designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Soft error derating computation in sequential circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Vulnerability analysis of L2 cache elements to single event upsets.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Soft Error Mitigation for SRAM-Based FPGAs.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Balancing Performance and Reliability in the Memory Hierarchy.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

An analytical approach for soft error rate estimation in digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Soft error rate estimation and mitigation for SRAM-based FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Soft Error Modeling and Protection for Sequential Elements.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

An Accurate SER Estimation Method Based on Propagation Probability.
Proceedings of the 2005 Design, 2005

2004
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

2003
Fault injection into SRAM-based FPGAs for the analysis of SEU effects.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

2002
Speedup analysis in simulation-emulation co-operation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Fast Prototyping with Co-operation of Simulation and Emulation.
Proceedings of the Field-Programmable Logic and Applications, 2002


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