Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. - Ming Yang 005; Shayan Shahramian; Hossein Shakiba; Henry Wong; Peter Krotnev; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan (ISSCC, 2021)

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications. - Jeremy Cosson-Martin; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2021)

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication. - Jhoan Salinas; Jeremy Cosson-Martin; Miad Laghaei; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2021)

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan; Davide Tonietto (IEEE J. Solid State Circuits, 2022)

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications. - Jeremy Cosson-Martin; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2022)

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier. - Milad Haghi Kashani; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2022)

Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE). - Mohammad Emami Meybodi; Hector Gomez; Yu-Chun Lu; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2022)

A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process. - Milad Haghi Kashani; Hossein Shakiba; Ali Sheikholeslami (ESSCIRC, 2023)

Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications. - Jeremy Cosson-Martin; Miad Laghaei; Hossein Shakiba; Ali Sheikholeslami (MWSCAS, 2023)

A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET. - Milad Haghi Kashani; Hossein Shakiba; Ali Sheikholeslami (VLSI Technology and Circuits, 2023)

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process. - Milad Haghi Kashani; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2023)

FBMC vs. PAM and DMT for High-Speed Wireline Communication. - Jeremy Cosson-Martin; Jhoan Salinas; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2024)

A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers. - Miad Laghaei; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2024)

Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication. - Mohammad Emami Meybodi; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2024)

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI. - Jhoan Salinas; Hossein Shakiba; Ali Sheikholeslami (IEEE Open J. Circuits Syst., 2024)

A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process. - Milad Haghi Kashani; Hossein Shakiba; Ali Sheikholeslami (IEEE J. Solid State Circuits, 2024)

MMSE Equalizer Design Optimization for Wireline SerDes Applications. - Alireza Akbarpour Bazargani; Hossein Shakiba; David A. Johns (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. - Richard Barrie; Ming Yang 005; Hossein Shakiba; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Max-Pooling PD: A Machine Learning-Based Timing Recovery Method. - Arash Hoseyninejad; Hossein Shakiba; David A. Johns (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)