Favorable Block First: A Comprehensive Cache Scheme to Accelerate Partial Stripe Recovery of Triple Disk Failure Tolerant Arrays. - Luyu Li; Houxiang Ji; Chentao Wu; Jie Li 002; Minyi Guo (ICPP, 2017)

ReCom: An efficient resistive accelerator for compressed deep neural networks. - Houxiang Ji; Linghao Song; Li Jiang 002; Hai Helen Li; Yiran Chen 001 (DATE, 2018)

HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. - Houxiang Ji; Li Jiang 002; Tianjian Li; Naifeng Jing; Jing Ke; Xiaoyao Liang (ASP-DAC, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (CoRR, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (PACT, 2020)

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Sara S. Baghsorkhi; Josep Torrellas (MICRO, 2020)

Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis. - Zirui Neil Zhao; Houxiang Ji; Mengjia Yan 001; Jiyong Yu; Christopher W. Fletcher; Adam Morrison 001; Darko Marinov; Josep Torrellas (MICRO, 2020)

Pinned loads: taming speculative loads in secure processors. - Zirui Neil Zhao; Houxiang Ji; Adam Morrison 001; Darko Marinov; Josep Torrellas (ASPLOS, 2022)

Comparative Reasoning for Knowledge Graph Fact Checking. - Lihui Liu; Houxiang Ji; Jiejun Xu; Hanghang Tong (IEEE Big Data, 2022)

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. - Zhangxiaowen Gong; Houxiang Ji; Yao Yao; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (ISCA, 2022)

Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. - Yan Sun; Yifan Yuan; Zeduo Yu; Reese Kuper; Chihun Song; Jinghan Huang 001; Houxiang Ji; Siddharth Agarwal; Jiaqi Lou; Ipoom Jeong; Ren Wang 001; Jung Ho Ahn; et al. (MICRO, 2023)

STYX: Exploiting SmartNIC Capability to Reduce Datacenter Memory Tax. - Houxiang Ji; Mark Mansi; Yan Sun; Yifan Yuan; Jinghan Huang 001; Reese Kuper; Michael M. Swift; Nam Sung Kim (USENIX ATC, 2023)

TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks. - Chihun Song; Michael Jaemin Kim; Tianchen Wang; Houxiang Ji; Jinghan Huang 001; Ipoom Jeong; Jaehyun Park 006; Hwayong Nam; Minbok Wi; Jung Ho Ahn; Nam Sung Kim (ASPLOS (3), 2024)

HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing. - Jinghan Huang 001; Jiaqi Lou; Srikar Vanavasam; Xinhao Kong; Houxiang Ji; Ipoom Jeong; Danyang Zhuo; Eun Kyung Lee; Nam Sung Kim (ISCA, 2024)

Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective. - Houxiang Ji; Srikar Vanavasam; Yang Zhou; Qirong Xia; Jinghan Huang 001; Yifan Yuan; Ren Wang 001; Pekon Gupta; Bhushan Chitlur; Ipoom Jeong; Nam Sung Kim (MICRO, 2024)

Para-ksm: Parallelized Memory Deduplication with Data Streaming Accelerator. - Houxiang Ji; Minho Kim; Seonmu Oh; Daehoon Kim; Nam Sung Kim (USENIX ATC, 2025)

Cooperative Memory Deduplication With Intel Data Streaming Accelerator. - Houxiang Ji; Minho Kim; Seonmu Oh; Daehoon Kim; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)

CABANA : Cluster-Aware Query Batching for Accelerating Billion-Scale ANNS With Intel AMX. - Minho Kim; Houxiang Ji; Jaeyoung Kang 004; Hwanjun Lee; Daehoon Kim; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)

Time Series Machine Learning Models for Precise SSD Access Latency Prediction. - Bikrant Das Sharma; Houxiang Ji; Ipoom Jeong; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)

X-PPR: Post Package Repair for CXL Memory. - Chihun Song; Michael Jaemin Kim; Yan Sun; Houxiang Ji; Kyungsan Kim; TaeKyeong Ko; Jung Ho Ahn; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)

Hardware-Accelerated Kernel-Space Memory Compression Using Intel QAT. - Qirong Xia; Houxiang Ji; Yang Zhou; Nam Sung Kim (IEEE Comput. Archit. Lett., 2025)