Cell Height Driven Transistor Sizing in a Cell Based Module Design. - How-Rern Lin; Ching-Lung Chou; Yu-Chin Hsu; TingTing Hwang (EDAC-ETC-EUROASIC, 1994)

Dynamical identification of critical paths for iterative gate sizing. - How-Rern Lin; TingTing Hwang (ICCAD, 1994)

Power recduction by gate sizing with path-oriented slack calculation. - How-Rern Lin; TingTing Hwang (ASP-DAC, 1995)

Cell height driven transistor sizing in a cell based static CMOS module design. - How-Rern Lin; Yu-Chin Hsu; TingTing Hwang (IEEE J. Solid State Circuits, 1996)

On determining sensitization criterion in an iterative gate sizing process. - How-Rern Lin; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. - How-Rern Lin; Wei-Hao Chiu; Tsung-Yi Wu (IEICE Trans. Electron., 2009)

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. - Tsung-Yi Wu; Tzi-Wei Kao; Shi-Yi Huang; Tai-Lun Li; How-Rern Lin (ASP-DAC, 2010)

Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. - Tsung-Yi Wu; Tzi-Wei Kao; How-Rern Lin (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)