A Parallel Architecture for Digital Filtering Using Fermat Number Transforms. - Trieu-Kien Truong; Irving S. Reed; C.-S. Yeh; Howard M. Shao (IEEE Trans. Computers, 1983)

VLSI residue multiplier modulo a Fermat number. - Irving S. Reed; Trieu-Kien Truong; Jaw John Chang; Howard M. Shao; In-Shek Hsu (IEEE Symposium on Computer Arithmetic, 1985)

A VLSI Design of a Pipeline Reed-Solomon Decoder. - Howard M. Shao; Trieu-Kien Truong; Leslie J. Deutsch; Joseph H. Yuen; Irving S. Reed (IEEE Trans. Computers, 1985)

VLSI Architectures for Computing Multiplications and Inverses in GF(2m). - Charles C. Wang; Trieu-Kien Truong; Howard M. Shao; Leslie J. Deutsch; Jim K. Omura; Irving S. Reed (IEEE Trans. Computers, 1985)

The VLSI design of a single chip for the multiplication of integers modulo a Fermat number. - Jaw John Chang; Trieu-Kien Truong; Howard M. Shao; Irving S. Reed; In-Shek Hsu (IEEE Trans. Acoust. Speech Signal Process., 1985)

A single chip VLSI Reed-Solomon decoder. - Howard M. Shao; Trieu-Kien Truong; In-Shek Hsu; Leslie J. Deutsch; Irving S. Reed (ICASSP, 1986)

On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays. - Howard M. Shao; Irving S. Reed (IEEE Trans. Computers, 1988)

A Pipeline Design of a Fast Prime Factor DFT on a Finite Field. - Trieu-Kien Truong; Irving S. Reed; In-Shek Hsu; Hsuen-Chyun Shyu; Howard M. Shao (IEEE Trans. Computers, 1988)