A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. - Hoyoung Tang; Gihoon Jung; Jongsun Park 001 (ISCAS, 2015)

Customized SRAM design for low power video code applications. - Sangkyu Lee; Hoyoung Tang; Kyungrak Choi; Jongsun Park 001 (ISOCC, 2016)

Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors. - Hoyoung Tang; Jongsun Park 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Spike Counts Based Low Complexity Learning with Binary Synapse. - Hoyoung Tang; Heetak Kim; Donghyeon Cho; Jongsun Park 001 (IJCNN, 2018)

Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications. - Juseong Lee; Hoyoung Tang; Jongsun Park 001 (IEEE Trans. Circuits Syst. Video Technol., 2018)

An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. - Heetak Kim; Hoyoung Tang; Jongsun Park 001 (ISLPED, 2019)

Spike Counts Based Low Complexity SNN Architecture With Binary Synapse. - Hoyoung Tang; Heetak Kim; Hyeonseong Kim; Jongsun Park 001 (IEEE Trans. Biomed. Circuits Syst., 2019)

Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates. - Hoyoung Tang; Donghyeon Cho; Dongwoo Lew; Taehwan Kim; Jongsun Park 001 (Neurocomputing, 2020)

An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability. - Heetak Kim; Hoyoung Tang; Woong Choi; Jongsun Park 001 (IEEE Trans. Biomed. Circuits Syst., 2020)

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. - Sangyeop Baeck; Inhak Lee; Hoyoung Tang; Dongwook Seo; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. - Jeongkyun Kim; Byungho Yook; Taemin Choi; Kyuwon Choi; Chanho Lee; Yunrong Li; Youngo Lee; Seok Yun; Changhoon Do; Hoyoung Tang; Inhak Lee; Dongwook Seo; et al. (VLSI Technology and Circuits, 2023)

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology. - Jeongkyun Kim; Byungho Yook; Youngo Lee; Taemin Choi; Kyuwon Choi; Chanho Lee; Juchang Lee; Hyeongcheol Kim; Seok Yun; Changhoon Do; Minwoo Kwak; Mijoung Kim; et al. (IEEE J. Solid State Circuits, 2024)