On Statistical Timing Analysis with Inter- and Intra-Die Variations. - Hratch Mangassarian; Mohab Anis (DATE, 2005)

Trace Compaction using SAT-based Reachability Analysis. - Sean Safarpour; Andreas G. Veneris; Hratch Mangassarian (ASP-DAC, 2007)

Maximum circuit activity estimation using pseudo-boolean satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Farid N. Najm; Magdy S. Abadir (DATE, 2007)

Improved Design Debugging Using Maximum Satisfiability. - Sean Safarpour; Hratch Mangassarian; Andreas G. Veneris; Mark H. Liffiton; Karem A. Sakallah (FMCAD, 2007)

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Marco Benedetti; Duncan Exon Smith (ICCAD, 2007)

A general framework for subjective information extraction from unstructured English text. - Hratch Mangassarian; Hassan Artail (Data Knowl. Eng., 2007)

A succinct memory model for automated design debugging. - Brian Keng; Hratch Mangassarian; Andreas G. Veneris (ICCAD, 2008)

QBF-Based Formal Verification: Experience and Perspectives. - Marco Benedetti; Hratch Mangassarian (J. Satisf. Boolean Model. Comput., 2008)

Leveraging dominators for preprocessing QBF. - Hratch Mangassarian; Bao Le; Alexandra Goultiaeva; Andreas G. Veneris; Fahiem Bacchus (DATE, 2010)

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. - Hratch Mangassarian; Andreas G. Veneris; Marco Benedetti (IEEE Trans. Computers, 2010)

Debugging with dominance: On-the-fly RTL debug solution implications. - Hratch Mangassarian; Andreas G. Veneris; Duncan Exon Smith; Sean Safarpour (ICCAD, 2011)

On error tolerance and Engineering Change with Partially Programmable Circuits. - Hratch Mangassarian; Hiroaki Yoshida; Andreas G. Veneris; Shigeru Yamashita; Masahiro Fujita (ASP-DAC, 2012)

Non-solution implications using reverse domination in a modern SAT-based debugging environment. - Bao Le; Hratch Mangassarian; Brian Keng; Andreas G. Veneris (DATE, 2012)

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Debugging RTL Using Structural Dominance. - Hratch Mangassarian; Bao Le; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)