Regular mapping for coarse-grained reconfigurable architectures. - Frank Hannig; Hritam Dutta; Jürgen Teich (ICASSP (5), 2004)

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. - Frank Hannig; Hritam Dutta; Jürgen Teich (IPDPS, 2004)

Co-Design of Massively Parallel Embedded Processor Architectures. - Frank Hannig; Hritam Dutta; Alexey Kupriyanov; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Ronan Keryell; Bernard Pottier; Daniel Chillet; Daniel Ménard; Olivier Sentieys (ReCoSoC, 2005)

Automatic FIR Filter Generation for FPGAs. - Holger Ruckdeschel; Hritam Dutta; Frank Hannig; Jürgen Teich (SAMOS, 2005)

Controller Synthesis for Mapping Partitioned Programs on Array Architectures. - Hritam Dutta; Frank Hannig; Jürgen Teich (ARCS, 2006)

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. - Hritam Dutta; Frank Hannig; Jürgen Teich; Benno Heigl; Heinz Hornegger (ASAP, 2006)

Hierarchical Partitioning for Piecewise Linear Algorithms. - Hritam Dutta; Frank Hannig; Jürgen Teich (PARELEC, 2006)

Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. - Frank Hannig; Hritam Dutta; Jürgen Teich (Int. J. Embed. Syst., 2006)

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. - Jürgen Teich; Frank Hannig; Holger Ruckdeschel; Hritam Dutta; Dmitrij Kissler; Andrej Stravet (ERSA, 2007)

Massively Parallel Processor Architectures: A Co-design Approach. - Hritam Dutta; Frank Hannig; Alexey Kupriyanov; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Bernard Pottier (ReCoSoC, 2007)

Efficient control generation for mapping nested loop programs onto processor arrays. - Hritam Dutta; Frank Hannig; Holger Ruckdeschel; Jürgen Teich (J. Syst. Archit., 2007)

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. - Frank Hannig; Holger Ruckdeschel; Hritam Dutta; Jürgen Teich (ARC, 2008)

Coarse-grained reconfiguration. - Sven Eisenhardt; Thomas Schweizer; Julio A. de Oliveira Filho; Tobias Oppold; Wolfgang Rosenstiel; Alexander Thomas; Jürgen Becker 001; Frank Hannig; Dmitrij Kissler; Hritam Dutta; Jürgen Teich; Heiko Hinkelmann; et al. (FPL, 2008)

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. - Hritam Dutta; Frank Hannig; Jürgen Teich (ARCS, 2009)

Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. - Frank Hannig; Hritam Dutta; Jürgen Teich (ARCS, 2009)

Impact of Loop Tiling on the Controller Logic of Acceleration Engines. - Hritam Dutta; Jiali Zhai; Frank Hannig; Jürgen Teich (ASAP, 2009)

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. - Richard Membarth; Philipp Kutzer; Hritam Dutta; Frank Hannig; Jürgen Teich (ASAP, 2009)

Model-based synthesis and optimization of static multi-rate image processing algorithms. - Joachim Keinert; Hritam Dutta; Frank Hannig; Christian Haubelt; Jürgen Teich (DATE, 2009)

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. - Richard Membarth; Frank Hannig; Hritam Dutta; Jürgen Teich (SAMOS, 2009)

A holistic approach for tightly coupled reconfigurable parallel processors. - Hritam Dutta; Dmitrij Kissler; Frank Hannig; Alexey Kupriyanov; Jürgen Teich; Bernard Pottier (Microprocess. Microsystems, 2009)

Modeling and synthesis of communication subsystems for loop accelerator pipelines. - Hritam Dutta; Frank Hannig; Moritz Schmid; Joachim Keinert (ASAP, 2010)

Synthesis and exploration of loop accelerators for systems-on-a-chip. - Hritam Dutta (2011)

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. - Richard Membarth; Hritam Dutta; Frank Hannig; Jürgen Teich (Trans. High Perform. Embed. Archit. Compil., 2019)