Efficient diagnosis of scan chains with single stuck-at faults. - Hsin-Chou Chi; Hsi-Che Tseng; Chih-Ling Yang (CISS, 2009)

Design of timing-error-resilient systolic arrays for matrix multiplication. - Hsin-Chou Chi; Hsi-Che Tseng; Kun-Lin Tsai (ISOCC, 2011)

Efficient diagnosable design of the IEEE P1500 architecture for SoC testing. - Hsin-Chou Chi; Hsi-Che Tseng; Chih-Ling Yang (NESEA, 2011)

Reconfigurable VLSI digital filters for tolerating multiple timing errors. - Hsin-Chou Chi; Hsi-Che Tseng; Chia-Wei Jeng (GCCE, 2013)

A high-performance VLSI architecture for variable block size motion estimation. - Hsin-Chou Chi; Han-Sheng Liu; Hsi-Che Tseng (GCCE, 2014)