A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator. - Hsi-En Liu; Shih-Che Hung; Chih-Wen Lu; Tsin-Yuan Chang (ISCAS, 2014)

Design and modeling of PLL-based clock and data recovery circuits with periodically embedded clock encoding for intra-panel interfaces. - Hsi-En Liu; Chun-Jen Su; Chih-Kang Cheng; Wen-Kuen Liu (ISCAS, 2016)