A pipeline ROM-less DDFS using equal-division interpolation. - Tsung-Yi Tsai; Hsiang-Yu Shih; Chua-Chin Wang (ISOCC, 2017)

74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; Hsiang-Yu Shih (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Power-effective ROM-less DDFS Design Approach with High SFDR Performance. - Chua-Chin Wang; Nanang Sulistiyanto; Hsiang-Yu Shih; Yu-Cheng Lin; Wei Wang (J. Signal Process. Syst., 2020)