Memory Latency Reduction via Thread Throttling. - Hsiang-Yun Cheng; Chung-Hsiang Lin; Jian Li; Chia-Lin Yang (MICRO, 2010)

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. - Hsiang-Yun Cheng; Matthew Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahmut T. Kandemir; Jack Sampson; Yuan Xie 001 (ISLPED, 2014)

Core vs. uncore: the heart of darkness. - Hsiang-Yun Cheng; Jia Zhan; Jishen Zhao; Yuan Xie 001; Jack Sampson; Mary Jane Irwin (DAC, 2015)

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. - Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahmut T. Kandemir; Jack Sampson; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2015)

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. - Hsiang-Yun Cheng; Mary Jane Irwin; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. - Hsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie 001 (ISCA, 2016)

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. - Meng-Fan Chang; Ching-Hao Chuang; Yen-Ning Chiang; Shyh-Shyuan Sheu; Chia-Chen Kuo; Hsiang-Yun Cheng; John Sampson; Mary Jane Irwin (ISCAS, 2016)

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. - Li Wang; Ren-Wei Tsai; Shao-Chung Wang; Kun-Chih Chen; Po-Han Wang 001; Hsiang-Yun Cheng; Yi-Chung Lee; Sheng-Jie Shu; Chun-Chieh Yang; Min-Yih Hsu; Li-Chen Kan; Chao-Lin Lee; et al. (ISPASS, 2017)

Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. - Li-Jhan Chen; Hsiang-Yun Cheng; Po-Han Wang 001; Chia-Lin Yang (IEEE Comput. Archit. Lett., 2017)

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. - Meng-Yao Lin; Hsiang-Yun Cheng; Wei-Ting Lin; Tzu-Hsien Yang; I-Ching Tseng; Chia-Lin Yang; Han-Wen Hu; Hung-Sheng Chang; Hsiang-Pang Li; Meng-Fan Chang (ICCAD, 2018)

LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. - Zhi-Lin Ke; Hsiang-Yun Cheng; Chia-Lin Yang (CoRR, 2018)

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. - Jörg Henkel; Hussam Amrouch; Martin Rapp; Sami Salamin; Dayane Reis; Di Gao; Xunzhao Yin; Michael T. Niemier; Cheng Zhuo; Xiaobo Sharon Hu; Hsiang-Yun Cheng; Chia-Lin Yang (ICCAD, 2019)

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. - Tzu-Hsien Yang; Hsiang-Yun Cheng; Chia-Lin Yang; I-Ching Tseng; Han-Wen Hu; Hung-Sheng Chang; Hsiang-Pang Li (ISCA, 2019)

TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. - Jing-Yuan Luo; Hsiang-Yun Cheng; Ing-Chao Lin; Da-Wei Chang (IEEE Trans. Computers, 2019)

GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. - Chin-Fu Nien; Yi-Jou Hsiao; Hsiang-Yun Cheng; Cheng-Yu Wen; Ya-Cheng Ko; Che-Ching Lin (DATE, 2020)

RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. - Chen-Yang Tsai; Chin-Fu Nien; Tz-Ching Yu; Hung-Yu Yeh; Hsiang-Yun Cheng (DAC, 2021)

Future Computing Platform Design: A Cross-Layer Design Approach. - Hsiang-Yun Cheng; Chun-Feng Wu; Christian Hakert; Kuan-Hsun Chen; Yuan-Hao Chang 001; Jian-Jia Chen; Chia-Lin Yang; Tei-Wei Kuo (DATE, 2021)

ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. - Yi-Jou Hsiao; Chin-Fu Nien; Hsiang-Yun Cheng (ICCD, 2021)

Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. - Zhi-Lin Ke; Hsiang-Yun Cheng; Chia-Lin Yang; Han-Wei Huang (ISPASS, 2021)

This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. - Yen-Ting Tsou; Kuan-Hsun Chen; Chia-Lin Yang; Hsiang-Yun Cheng; Jian-Jia Chen; Der-Yu Tsai (ASP-DAC, 2022)

RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment. - Ting Wu; Chin-Fu Nien; Kuang-Chao Chou; Hsiang-Yun Cheng (DATE, 2022)

Efficient Bad Block Management with Cluster Similarity. - Jui-Nan Yen; Yao-Ching Hsieh; Cheng-Yu Chen; Tseng-Yi Chen; Chia-Lin Yang; Hsiang-Yun Cheng; Yixin Luo (HPCA, 2022)

Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement. - He-Sheng Chou; Hsiang-Yun Cheng; Jun-Xiang Qiu; Tsun-Kuang Chi; Tsung-Yi Chen; Shin-Lun Chen (ICCE, 2022)

Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. - Nai-Jia Dong; Hsiang-Yun Cheng; Chia-Lin Yang; Bo-Rong Lin; Hsiang-Pang Li (NVMSA, 2022)

DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. - Wei-Ting Lin; Hsiang-Yun Cheng; Chia-Lin Yang; Meng-Yao Lin; Kai Lien; Han-Wen Hu; Hung-Sheng Chang; Hsiang-Pang Li; Meng-Fan Chang; Yen-Ting Tsou; Chin-Fu Nien (ACM Trans. Embed. Comput. Syst., 2022)

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. - Jörg Henkel; Lokesh Siddhu; Lars Bauer; Jürgen Teich; Stefan Wildermann; Mehdi B. Tahoori; Mahta Mayahinia; Jerónimo Castrillón; Asif Ali Khan; Hamid Farzaneh; João Paulo C. de Lima; Jian-Jia Chen; et al. (CASES, 2023)

Tensor Movement Orchestration in Multi-GPU Training Systems. - Shao-Fu Lin; Yi-Jung Chen; Hsiang-Yun Cheng; Chia-Lin Yang (HPCA, 2023)

BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. - Chi-Tse Huang; Cheng-Yang Chang; Hsiang-Yun Cheng; An-Yeu Wu (DATE, 2024)

ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems. - Hao-Wei Chiang; Chin-Fu Nien; Hsiang-Yun Cheng; Kuei-Po Huang (ISCA, 2024)

Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. - Hao-Wei Chiang; Chi-Tse Huang; Hsiang-Yun Cheng; Po-Hao Tseng; Ming-Hsiu Lee; An-Yeu Andy Wu (ASP-DAC, 2025)

ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. - Tsung-Yu Liu; Yen-An Lu; James Yu; Chin-Fu Nien; Hsiang-Yun Cheng (ASP-DAC, 2025)

In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. - You-Kai Zheng; Ming-Liang Wei; Hsiang-Yun Cheng; Chia-Lin Yang; Ming-Hsiang Tsai; Chia-Chun Chien; Yuan-Hao Zhong; Po-Hao Tseng; Hsiang-Pang Li (ASP-DAC, 2025)

Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. - Jing-Jia Hung; Yi-Jung Chen; Hsiang-Yun Cheng; Hsu Kao; Chia-Lin Yang (DATE, 2025)