Top-down modeling of RISC processors in VHDL. - Hsiao-Ping Juan; Nancy D. Holmes; Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1993)

Condition graphs for high-quality behavioral synthesis. - Hsiao-Ping Juan; Viraphol Chaiyakul; Daniel D. Gajski (ICCAD, 1994)

Component selection in resource shared and pipelined DSP applications. - Smita Bakshi; Daniel D. Gajski; Hsiao-Ping Juan (EURO-DAC, 1996)

Clock optimization for high-performance pipelined design. - Hsiao-Ping Juan; Smita Bakshi; Daniel D. Gajski (EURO-DAC, 1996)

Clock-driven performance optimization in interactive behavioral synthesis. - Hsiao-Ping Juan; Daniel Gajski; Viraphol Chaiyakul (ICCAD, 1996)