A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. - Xiaoyu Sun 001; Rui Liu 005; Yi-Ju Chen; Hsiao-Yun Chiu; Wei-Hao Chen; Meng-Fan Chang; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2017)