A (208, 192;8) Reed-Solomon decoder for DVD application. - Hsie-Chia Chang; C. Bernard Shung (ICC, 1998)

New serial architecture for the Berlekamp-Massey algorithm. - Hsie-Chia Chang; C. Bernard Shung (IEEE Trans. Commun., 1999)

An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. - Hsie-Chia Chang; Chen-Yi Lee (ISCAS (2), 2001)

A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. - Hsie-Chia Chang; C. Bernard Shung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2001)

A Low-Power Design for Reed-Solomon Decoders. - Hsie-Chia Chang; Chen-Yi Lee (J. Circuits Syst. Comput., 2003)

A dual mode channel decoder for 3GPP2 mobile wireless communications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2004)

Multi-level memory systems using error control codes. - Hsie-Chia Chang; Chien-Ching Lin; Tien-Yuan Hsiao; Jieh-Tsorng Wu; Ta-Hui Wang (ISCAS (2), 2004)

A power and area efficient multi-mode FEC processor. - Yi-Chen Tseng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (ISCAS (2), 2004)

A 3.33Gb/s (1200,720) low-density parity check code decoder. - Chien-Ching Lin; Kai-Li Lin; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2005)

Design of a power-reduction Viterbi decoder for WLAN applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A self-compensation fixed-width booth multiplier and its 128-point FFT applications. - Hong-An Huang; Yen-Chin Liao; Hsie-Chia Chang (ISCAS, 2006)

Carry Estimation for Two's Complement Fixed-Width Multipliers. - Yen-Chin Liao; Hsie-Chia Chang; Chih-Wei Liu (SiPS, 2006)

A low power turbo/Viterbi decoder for 3GPP2 applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. - Cheng-Chi Wong; Cheng-Hao Tang; Ming-Wei Lai; Yan-Xiu Zheng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yu.-T. Su (CICC, 2007)

Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems. - Hsiu-Chi Chang; Yen-Chin Liao; Hsie-Chia Chang (SiPS, 2007)

Self-Compensation Technique for Simplified Belief-Propagation Algorithm. - Yen-Chin Liao; Chien-Ching Lin; Hsie-Chia Chang; Chih-Wei Liu (IEEE Trans. Signal Process., 2007)

Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints. - Yi Hsuan Wu; Yu Ting Liu; Hsiu-Chi Chang; Yen-Chin Liao; Hsie-Chia Chang (ICC, 2008)

Structured LDPCcodes with low error floor based on PEG tanner graphs. - Yi-Kai Lin; Chin-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang (ISCAS, 2008)

Multi-mode message passing switch networks applied for QC-LDPC decoder. - Chih-Hao Liu; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yarsun Hsua (ISCAS, 2008)

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. - Chih-Hao Liu; Shau-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. - Shao-Wei Yen; Ming-Chih Hu; Chin-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (CICC, 2009)

A 11.5-Gbps LDPC decoder based on CP-PEG code construction. - Chih-Lung Chen; Kao-Shou Lin; Hsie-Chia Chang; Wai-Chi Fang; Chen-Yi Lee (ESSCIRC, 2009)

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2009)

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. - Hsie-Chia Chang; Chien-Ching Lin; Fu-Ke Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. - Chih-Hao Liu; Chien-Ching Lin; Shao-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. - Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee (APCCAS, 2010)

A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. - Jen-Wei Lee; Yao-Lin Chen; Chih-Yeh Tseng; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2010)

An improved soft BCH decoder with one extra error compensation. - Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2010)

A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (ISCAS, 2010)

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. - Po-Tsang Huang; Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee; Wei Hwang (J. Low Power Electron., 2010)

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. - Yi-Min Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. - Cheng-Chi Wong; Ming-Wei Lai; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. - Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. - Po-Chun Liu; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2011)

A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. - Yao-Lin Chen; Jen-Wei Lee; Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2011)

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. - Yi-Min Lin; Chi-Heng Yang; Chih-Hsiang Hsu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. - Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (APCCAS, 2012)

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (CHES, 2012)

A fully parallel BCH codec with double error correcting capability for NOR flash applications. - Chia-Ching Chu; Yi-Min Lin; Chi-Heng Yang; Hsie-Chia Chang (ICASSP, 2012)

A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. - Szu-Chi Chung; Jen-Wei Lee; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

Stochastic decoding for LDPC convolutional codes. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

An improved LT encoding scheme with extended chain lengths. - Kuo-Kuang Yen; Chih-Lung Chen; Hsie-Chia Chang (ISITA, 2012)

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. - Yi-Hsun Chen; Chi-Heng Yang; Hsie-Chia Chang (VLSI-DAT, 2012)

A low cost DPA-resistant 8-bit AES core based on ring oscillators. - Hsing-Ping Fu; Ju-Hung Hsiao; Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (VLSI-DAT, 2012)

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. - Chih-Lung Chen; Yu-Hsiang Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. - Shao-Wei Yen; Shiang-Yu Hung; Chih-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. - Jen-Wei Lee; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. - Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

An area-efficient BCH codec with echelon scheduling for NAND flash applications. - Chi-Heng Yang; Yi-Hsun Chen; Hsie-Chia Chang (ICC, 2013)

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. - Kin-Chu Ho; Po-Chao Fang; Hsiang-Pang Li; Cheng-Yuan Michael Wang; Hsie-Chia Chang (ISSCC, 2013)

Processor with side-channel attack resistance. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (ISSCC, 2013)

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (WCSP, 2013)

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. - Hsiu-Chi Chang; Chih-Lung Chen; Hsie-Chia Chang (IEEE Commun. Lett., 2013)

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (IEEE Commun. Lett., 2013)

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (IEEE J. Solid State Circuits, 2013)

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; John K. Zao; Hsie-Chia Chang (IEEE Trans. Multim., 2013)

Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. - Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. - Chih-Lung Chen; Sheng-Jhan Wu; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2014)

A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. - Kelvin Yi-Tse Lai; Yu-Tao Yang; Bang-Jing Chen; Chun-Jen Shen; Ming-Feng Shiu; Zih-Cheng He; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2014)

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. - Chih-Wen Yang; Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2014)

Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes. - Hsiu-Chi Chang; Hsie-Chia Chang (ISTC, 2014)

A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. - Chang-Hung Tsai; Tung-Yu Wu; Shu-Yu Hsu; Chia-Ching Chu; Fang-Ju Ku; Ying-Siou Laio; Chih-Lung Chen; Wing Hung Wong; Hsie-Chia Chang; Chen-Yi Lee (VLSIC, 2014)

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. - Yi-Min Lin; Chih-Hsiang Hsu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes. - Hsiu-Chi Chang; Hsie-Chia Chang (IEEE Trans. Commun., 2014)

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. - Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. - Kelvin Yi-Tse Lai; Ming-Feng Shiu; Yi-Wen Lu; Yingchieh Ho; Yu-Chi Kao; Yu-Tao Yang; Gary Wang; Keng-Ming Liu; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2015)

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2015)

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. - Kin-Chu Ho; Chih-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2015)

Design of LT code degree distribution with profiled output ripple size. - Kuo-Kuang Yen; Yen-Chin Liao; Hsie-Chia Chang (SiPS, 2015)

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. - Chia-Lung Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. - Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. - Szu-Chi Chung; Jing-Yu Wu; Hsing-Ping Fu; Jen-Wei Lee; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. - Chi-Heng Yang; Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. - Chia-Lung Lin; Rong-Jie Liu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2016)

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. - Chia-Lung Lin; Shu-Wen Tu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. - Kin-Chu Ho; Chih-Lung Chen; Hsie-Chia Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Re-Polarization Processing in Extended Polar Codes. - Yu-Ming Huang; Hsie-Chia Chang; Hsiang-Pang Li (IEICE Trans. Commun., 2017)

An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. - Szu-Chi Chung; Chun-Yuan Yu; Sung-Shine Lee; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A. - Po-Hsun Chang; Chen-Yang Lin; Chia-Hsiang Sun; Yen-Chin Liao; Hsie-Chia Chang (ISCAS, 2018)

Scalable Globally-Coupled Low-Density Parity Check Codes. - Yen-Chin Liao; Hsie-Chia Chang; Shu Lin 001 (ISTC, 2018)

Generalized Globally-Coupled Low-Density Parity-Check Codes. - Yen-Chin Liao; Hsie-Chia Chang; Shu Lin 001 (ITW, 2018)

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. - Fang-Ju Ku; Tung-Yu Wu; Yen-Chin Liao; Hsie-Chia Chang; Wing Hung Wong; Chen-Yi Lee (VLSI-DAT, 2018)

ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation. - Wei-Chien Kuo; Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang (SoCC, 2019)

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. - Yun-Wen Lu; Antoon Purnal; Simon Vandenhende; Chen-Yi Lee; Ingrid Verbauwhede; Hsie-Chia Chang (VLSI-DAT, 2019)

A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications. - Yen-Chin Liao; Chien Lin; Hsie-Chia Chang; Shu Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. - Yi-An Chen; Gung-Yu Pan; Che-Hua Shih; Yen-Chin Liao; Chia-Chih Yen; Hsie-Chia Chang (DATE, 2020)

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. - Wei Chiang; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2020)

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). - Tony Chan Carusone; Mingoo Seok; Hsie-Chia Chang; Meng-Fan Chang (IEEE J. Solid State Circuits, 2020)

A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network. - Ya-Yun Hou; Shaopeng Lai; Hung-Kun Chang; Yun-Wen Lu; Hsie-Chia Chang (A-SSCC, 2021)

A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. - Chieh-Yu Lin; Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang (ISCAS, 2021)

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. - Sukhwan Lim; Yongpan Liu; Luca Benini; Tanay Karnik; Hsie-Chia Chang (ISSCC, 2021)

A Two-Stage Path Planning Engine for Robot Navigation System. - Yu-En Hsu; Yen-Chin Liao; Hsie-Chia Chang (SoCC, 2021)

An Attention-based Neural Network on Multiple Speaker Diarization. - Shao Wen Cheng; Kai Jyun Hung; Hsie-Chia Chang; Yen-Chin Liao (AICAS, 2022)

A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND. - Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang (ICASSP, 2022)

UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications. - Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang (IEEE Open J. Circuits Syst., 2022)

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories. - Li-Wei Liu; Mu-Hua Yuan; Yen-Chin Liao; Hsie-Chia Chang (IEEE Open J. Circuits Syst., 2022)

A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation. - Xiao-Juan Huang; Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang; Sau-Gee Chen (APCCAS, 2023)

GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation. - Yu-Lun Hsu; Li-Wei Liu; Yen-Chin Liao; Hsie-Chia Chang (IEEE Open J. Circuits Syst., 2024)