SRAM Cell Current in Low Leakage Design. - Ding-Ming Kwai; Ching-Hua Hsiao; Chung-Ping Kuo; Chi-Hsien Chuang; Min-Chung Hsu; Yi-Chun Chen; Yu-Ling Sung; Hsien-Yu Pan; Chia-Hsin Lee; Meng-Fan Chang; Yung-Fa Chou (MTDT, 2006)

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. - Yen-Huei Chen; Gary Chan; Shao-Yu Chou; Hsien-Yu Pan; Jui-Jen Wu; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2009)

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. - Hidehiro Fujiwara; Chih-Yu Lin; Hsien-Yu Pan; Cheng-Han Lin; Po-Yi Huang; Kao-Cheng Lin; Jhon-Jhy Liaw; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2019)

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. - Hidehiro Fujiwara; Yi-Hsin Nien; Chih-Yu Lin; Hsien-Yu Pan; Hao-Wen Hsu; Shin-Rung Wu; Yao-Yi Liu; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2021)