Design formula for band-switching capacitor array in wide tuning range low-phase-noise LC-VCO. - Hwann-Kaeo Chiou; Hsien-Jui Chen; Hsien-Yuan Liao; Shuw-Guann Lin; Yin-Cheng Chang (Microelectron. J., 2008)

Harmonic Control Network for 2.6 GHz CMOS Class-F Power Amplifier. - Hsien-Yuan Liao; Jhih-Hong Chen; Hwann-Kaeo Chiou; Shih-Ming Wang (ISCAS, 2009)

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. - Feng-Wei Kuo; Huan-Neng Ron Chen; Kyle Yen; Hsien-Yuan Liao; Chewnpu Jou; Fu-Lung Hsueh; Masoud Babaie; Robert Bogdan Staszewski (VLSIC, 2014)

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. - Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Yu-Tso Lin; Tsung-Hsien Tsai; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Augusto Ronchini Ximenes; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)