An improved BJT-based silicon retina with tunable image smoothing capability. - Chung-Yu Wu; Hsin-Chin Jiang (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. - Ming-Dou Ker; Hsin-Chin Jiang; Jeng-Jie Peng; Tzay-Luen Shieh (ICECS, 2001)

ESD test methods on integrated circuits: an overview. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ICECS, 2001)

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. - Jeng-Jie Peng; Ming-Dou Ker; Hsin-Chin Jiang (ISCAS (5), 2002)

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. - Ming-Dou Ker; Jeng-Jie Peng; Hsin-Chin Jiang (ISQED, 2003)