Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers. - Hsin-Chou Chi; Yuval Tamir (ICCD, 1991)

Symmetric Crossbar Arbiters for VLSI Communication Switches. - Yuval Tamir; Hsin-Chou Chi (IEEE Trans. Parallel Distributed Syst., 1993)

Starvation Prevention for Arbiters of Crossbars with Multi-Queue Input Buffers. - Hsin-Chou Chi; Yuval Tamir (COMPCON, 1994)

A Deadlock-Free Routing Scheme for Interconnection Networks with Irregular Topologies. - Hsin-Chou Chi; Chih-Tsung Tang (ICPADS, 1997)

Routing Tree Construction for Interconnection Network with Irregular Topologies. - Hsin-Chou Chi; Wen-Jen Wu (PDP, 2003)

Efficient Switches for Network-on-Chip Based Embedded Systems. - Hsin-Chou Chi; Chia-Ming Wu (EUC, 2005)

A Switch Supporting Circuit and Packet Switching for On-Chip Networks. - Hsin-Chou Chi; Chia-Ming Wu; Sung-Tze Wu (DDECS, 2006)

An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures. - Hsin-Chou Chi; Chia-Ming Wu (VLSI-SoC, 2006)

Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. - Hsin-Chou Chi; Chia-Ming Wu; Jun-Hui Lee (DELTA, 2008)

Efficient diagnosis of scan chains with single stuck-at faults. - Hsin-Chou Chi; Hsi-Che Tseng; Chih-Ling Yang (CISS, 2009)

Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology. - Hsin-Chou Chi; Yu-Hong Jhang; Wen-Shu Chen (ISVLSI, 2010)

Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks. - Hsin-Chou Chi; Tat-Seng Chang; Chia-Ming Wu (SIES, 2010)

Design of timing-error-resilient systolic arrays for matrix multiplication. - Hsin-Chou Chi; Hsi-Che Tseng; Kun-Lin Tsai (ISOCC, 2011)

Efficient diagnosable design of the IEEE P1500 architecture for SoC testing. - Hsin-Chou Chi; Hsi-Che Tseng; Chih-Ling Yang (NESEA, 2011)

Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores. - Hsin-Chou Chi; Jr-Fen Ferng; Yu-Chen Hsieh (HPCC-ICESS, 2012)

Reconfigurable VLSI digital filters for tolerating multiple timing errors. - Hsin-Chou Chi; Hsi-Che Tseng; Chia-Wei Jeng (GCCE, 2013)

A high-performance VLSI architecture for variable block size motion estimation. - Hsin-Chou Chi; Han-Sheng Liu; Hsi-Che Tseng (GCCE, 2014)