A high-performance area-aware DSP processor architecture for video codecs. - Lan-Da Van; Hsin-Fu Luo; Chien-Ming Wu; Wen-Hsiang Hu; Chun-Ming Huang; Wei-Chang Tsai (ICME, 2004)

A cost-effective reconfigurable accelerator for platform-based SOC design. - Lan-Da Van; Hsin-Fu Luo; Nien-Hsiang Chang; Chun-Ming Huang (ISCAS, 2006)

Efficient memory management for FFT processors. - Hsin-Fu Luo; Ming-Der Shieh; Yi-Jun Liu; Chien-Ming Wu (ISCAS, 2010)

Efficient memory management scheme for pipelined shared-memory FFT processors. - Hsin-Fu Luo; Ming-Der Shieh (ICCE-TW, 2015)

A radix-2/3/22/23 MDC architecture for variable-length FFT processors. - Hsin-Fu Luo; Ming-Der Shieh; Kun-Hsien Lee (ICCE-TW, 2015)

Efficient Memory-Addressing Algorithms for FFT Processor Design. - Hsin-Fu Luo; Yi-Jun Liu; Ming-Der Shieh (IEEE Trans. Very Large Scale Integr. Syst., 2015)