A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies. - Yu-Jie Huang; Mu-Shan Lin; Chien-Chun Tsai; Wei-Chih Chen; Hsin-Hung Kuo; Shu-Chun Yang; Shenggao Li (CICC, 2025)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)